Register Sharing for Equality Prediction

Arthur Perais 1 Fernando A. Endo 1 André Seznec 1
1 PACAP - Pushing Architecture and Compilation for Application Performance
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Abstract : —Recently, Value Prediction (VP) has been gaining renewed traction in the research community. VP speculates on the result of instructions to increase Instruction Level Parallelism (ILP). In most embodiments, VP requires large tables to track predictions for many static instructions. However, in many cases, it is possible to detect that the result of an instruction is produced by an older inflight instruction, but not to predict the result itself. Consequently it is possible to rely on predicting register equality and handle speculation through the renamer. To do so, we propose to use Distance Prediction, a technique that was previously used to perform Speculative Memory Bypassing (short-circuiting def-store-load-use chains). Distance Prediction attempts to determine how many instructions separate the instruction of interest and the most recent older instruction that produced the same result. With this information, the physical register identifier of the older instruction can be retrieved from the ROB and provided to the renamer. In this paper, we first quantify the performance gains brought by renaming-based register equality prediction and regular VP on SPEC benchmarks. Second, we study the overlap between the two different schemes and show that those mechanisms often capture different behavior.
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Communication dans un congrès
International Symposium on Microarchitecture, Oct 2016, Taipei, Taiwan. 2016, 〈http://www.microarch.org/micro49/〉
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Dernière modification le : mardi 16 janvier 2018 - 15:54:26

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  • HAL Id : hal-01354267, version 1

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Arthur Perais, Fernando A. Endo, André Seznec. Register Sharing for Equality Prediction. International Symposium on Microarchitecture, Oct 2016, Taipei, Taiwan. 2016, 〈http://www.microarch.org/micro49/〉. 〈hal-01354267〉

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