The Instruction-Set Extension Problem, ACM Transactions on Reconfigurable Technology and Systems, vol.4, issue.2, pp.209-220, 2008. ,
DOI : 10.1145/1968502.1968509
Automatic applicationspecific instruction-set extensions under microarchitectural constraints, pp.256-261, 2003. ,
Exact and approximate algorithms for the extension of embedded processor instruction sets, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.25, issue.7, pp.1209-1229, 2006. ,
DOI : 10.1109/TCAD.2005.855950
An efficient algorithm for custom instruction enumeration. GLSVLSI, pp.187-192, 2011. ,
URL : https://hal.archives-ouvertes.fr/hal-00746760
Exact custom instruction enumeration for extensible processors, Integration, the VLSI Journal, vol.45, issue.3, pp.263-270, 2012. ,
DOI : 10.1016/j.vlsi.2011.11.011
URL : https://hal.archives-ouvertes.fr/hal-00746877
Fast Identification of Custom Instructions for Extensible Processors, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.26, issue.2, pp.359-368, 2007. ,
DOI : 10.1109/TCAD.2006.883915
Polynomial-Time Subgraph Enumeration for Automated Instruction Set Extension, 2007 Design, Automation & Test in Europe Conference & Exhibition, pp.1331-1336, 2007. ,
DOI : 10.1109/DATE.2007.364482
Fast enumeration of maximal valid subgraphs for custom-instruction identification, Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems, CASES '09, pp.29-36, 2009. ,
DOI : 10.1145/1629395.1629402
Fast, Nearly Optimal ISE Identification With I/O Serialization Through Maximal Clique Enumeration, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.29, issue.3, pp.341-354, 2010. ,
DOI : 10.1109/TCAD.2010.2041849
Complexity of Computing Convex Subgraphs in Custom Instruction Synthesis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.2012-2337 ,
DOI : 10.1109/TVLSI.2011.2173221
Scalable subgraph mapping for acyclic computation accelerators, Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems , CASES '06, pp.147-157, 2006. ,
DOI : 10.1145/1176760.1176779
Application-specific instruction generation for configurable processor architectures, Proceeding of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays , FPGA '04, pp.183-189, 2004. ,
DOI : 10.1145/968280.968307
Satisfying real-time constraints with custom instructions, CODES+ISSS, pp.166-171, 2005. ,
Automatic selection of application-specific instructionset extensions, CODES+ISSS, pp.160-165, 2006. ,
An integer linear programming approach for identifying instruction-set extensions, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES+ISSS '05, pp.172-177, 2005. ,
DOI : 10.1145/1084834.1084880
Charot: Constraint Programming Approach to Reconfigurable Processor Extension Generation and Application Compilation, TRET- S, vol.5, issue.2, p.2012 ,
Instruction Selection and Scheduling for DSP Kernels on Custom Architectures, 2013 Euromicro Conference on Digital System Design, pp.821-828, 2013. ,
DOI : 10.1109/DSD.2013.91
Instruction generation for hybrid reconfigurable systems, ACM Transactions on Design Automation of Electronic Systems, vol.7, issue.4, pp.605-627, 2002. ,
DOI : 10.1145/605440.605446
Automatic Selection of Application-Specific Reconfigurable Processor Extensions, pp.1214-1219, 2008. ,
URL : https://hal.archives-ouvertes.fr/inria-00451683
Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization, 37th International Symposium on Microarchitecture (MICRO-37'04), pp.30-40, 2004. ,
DOI : 10.1109/MICRO.2004.5
Selecting profitable custom instructions for reconfigurable processors, Journal of Systems Architecture, vol.56, issue.8, pp.340-351, 2010. ,
DOI : 10.1016/j.sysarc.2010.04.004
Dual-purpose custom instruction identification algorithm based on Particle Swarm Optimization, ASAP 2010, 21st IEEE International Conference on Application-specific Systems, Architectures and Processors, pp.159-166, 2010. ,
DOI : 10.1109/ASAP.2010.5541012
Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.29, issue.6, pp.911-924, 2010. ,
DOI : 10.1109/TCAD.2010.2048354
Instruction set extension exploration in multiple-issue architecture, DATE, pp.764-769, 2008. ,
Multi-objective Application-specific Instruction set Processor Design: Towards High Performance, Energyefficient , and Secure Embedded Systems Doctoral Dissertations, 2011. ,
FISH: Fast Instruction SyntHesis for Custom Processors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.2012-52 ,
DOI : 10.1109/TVLSI.2010.2090543
A graph covering algorithm for a coarse grain reconfigurable system, LCTES, pp.199-208, 2003. ,
On cliques in graphs, Israel Journal of Mathematics, vol.3, issue.1, pp.23-28, 1965. ,
DOI : 10.1007/BF02760024
Optimization by Simulated Annealing, Science, vol.220, issue.4598, pp.671-680, 1983. ,
DOI : 10.1126/science.220.4598.671
Tabu search: A tutorial. Interfaces, pp.74-94, 1990. ,
Comparing three heuristic search methods for functional partitioning in hardware-software codesign, Design Automation for Embedded Systems, vol.6, issue.4, pp.425-449, 2002. ,
DOI : 10.1023/A:1016567828852
Adaptation in natural and artificial systems, Univ., 1975. ,
Particle swarm optimization, Proceedings of ICNN'95, International Conference on Neural Networks, pp.1942-1948, 1995. ,
DOI : 10.1109/ICNN.1995.488968
Ant system: optimization by a colony of cooperating agents, IEEE Transactions on Systems, Man and Cybernetics, Part B (Cybernetics), vol.26, issue.1, pp.29-41, 1996. ,
DOI : 10.1109/3477.484436
Generic compiler suite -http://gecos.gforge.inria ,
MiBench: A free, commercially representative embedded benchmark suite, Proceedings of the Fourth Annual IEEE International Workshop on Workload Characterization. WWC-4 (Cat. No.01EX538), pp.3-14, 2001. ,
DOI : 10.1109/WWC.2001.990739
Mediabench: A tool for evaluating and synthesizing multimedia and communications systems, pp.330-335, 1997. ,
Intelligent optimisation techniques: genetic algorithms, tabu search, simulated annealing and neural networks, 2012. ,
DOI : 10.1007/978-1-4471-0721-7