Skip to Main content Skip to Navigation
Conference papers

Gate Sizing Under Uncertainty

Abstract : We present a gate sizing approach to efficiently utilize gate switching activity (SA) and gate input vector control leakage (IVC) uncertainty factors in the objective function in order enable more efficient power and speed yield trade-offs. Our algorithm conducts iterative gate freezing and unlocking with cut-based search for the most beneficial gate sizes under delay constraints. In an iterative flow, we interchangeably conduct gate sizing and IVC refinement to adapt to new circuit configurations. We evaluate our approach on benchmarks in 45 nm technology and demonstrate up to 62 % (29 % avg.) energy savings compared to a traditional objective function that does not consider SA and IVC. We further adapt our approach to optimize yield objectives by addressing processing variation (PV). Significant improvements were achieved under identical timing yield targets of up to 84 % max (55 % avg.) and 74 % max (25 % avg.) mean-power savings for selected ISCAS-85 and ITC-99 benchmarks, respectively.
Document type :
Conference papers
Complete list of metadata

Cited literature [17 references]  Display  Hide  Download

https://hal.inria.fr/hal-01380297
Contributor : Hal Ifip <>
Submitted on : Wednesday, October 12, 2016 - 5:38:52 PM
Last modification on : Thursday, March 5, 2020 - 5:40:12 PM
Long-term archiving on: : Saturday, February 4, 2017 - 8:31:19 PM

File

367527_1_En_2_Chapter.pdf
Files produced by the author(s)

Licence


Distributed under a Creative Commons Attribution 4.0 International License

Identifiers

Citation

Nathaniel Conos, Saro Meguerdichian, Miodrag Potkonjak. Gate Sizing Under Uncertainty. 21th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2013, Istanbul, Turkey. pp.23-47, ⟨10.1007/978-3-319-23799-2_2⟩. ⟨hal-01380297⟩

Share

Metrics

Record views

112

Files downloads

402