E. Artzy, J. A. Hinds, and H. J. Saal, A fast division technique for constant divisors, Communications of the ACM, vol.19, issue.2, pp.98-101, 1976.
DOI : 10.1145/359997.360013

F. De-dinechin, Multiplication by Rational Constants, IEEE Transactions on Circuits and Systems II: Express Briefs, vol.59, issue.2, pp.98-102, 2012.
DOI : 10.1109/TCSII.2011.2177706
URL : https://hal.archives-ouvertes.fr/ensl-00610328

T. Drane, W. C. Cheung, and G. Constantinides, Correctly rounded constant integer division via multiply-add, 2012 IEEE International Symposium on Circuits and Systems, pp.1243-1246, 2012.
DOI : 10.1109/ISCAS.2012.6271461

S. R. Li, Fast constant division routines, IEEE Transactions on Computers, vol.34, issue.9, pp.866-869, 1985.

P. Srinivasan and F. E. Petry, Constant-division algorithms, Proc. Computers and Digital Techniques, pp.334-340, 1994.
DOI : 10.1049/ip-cdt:19941414

R. W. Doran, Special Cases of Division, Journal of Universal Computer Science, vol.1, issue.3, pp.67-82, 1995.
DOI : 10.1007/978-3-642-80350-5_16

F. De-dinechin and L. Didier, Table-Based Division by Small Integer Constants, Int. Symp. on Applied Reconfigurable Computing (ARC), pp.53-63, 2012.
DOI : 10.1049/ip-cdt:19941414
URL : https://hal.archives-ouvertes.fr/ensl-00642145

A. Paplinski, CSE2306/1308 Digital Logic Lecture Note, 2006.

A. D. Robison, N-Bit Unsigned Division via N-Bit Multiply-Add, 17th IEEE Symposium on Computer Arithmetic (ARITH'05), pp.131-139, 2005.
DOI : 10.1109/ARITH.2005.31
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.512.2627

N. Brisebarre, J. Muller, and S. K. Raina, Accelerating correctly rounded floating-point division when the divisor is known in advance, IEEE Transactions on Computers, vol.53, issue.8, pp.1069-1072, 2004.
DOI : 10.1109/TC.2004.37

H. F. Ugurdag, A. Bayram, V. E. Levent, and S. , Efficient Combinational Circuits for Division by Small Integer Constants, 2016 IEEE 23nd Symposium on Computer Arithmetic (ARITH), pp.1-7, 2016.
DOI : 10.1109/ARITH.2016.23

M. Istoan and F. De-dinechin, Automating the pipeline of arithmetic datapaths, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017.
DOI : 10.23919/DATE.2017.7927080
URL : https://hal.archives-ouvertes.fr/hal-01373937

N. Brisebarre, F. De-dinechin, and J. Muller, Integer and floating-point constant multipliers for FPGAs, 2008 International Conference on Application-Specific Systems, Architectures and Processors, pp.239-244, 2008.
DOI : 10.1109/ASAP.2008.4580184
URL : https://hal.archives-ouvertes.fr/ensl-00269219

M. Kumm, Multiple constant multiplication optimizations for field programmable gate arrays, 2016.
DOI : 10.1007/978-3-658-13323-8

K. D. Chapman, Fast integer multipliers fit in FPGAs (EDN 1993 design idea winner), " EDN magazine, p.80, 1993.

M. J. Wirthlin, Constant Coefficient Multiplication Using Look-Up Tables, The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, vol.36, issue.1, pp.7-15, 2004.
DOI : 10.1023/B:VLSI.0000008066.95259.b8

O. Gustafsson, Lower Bounds for Constant Multiplication Problems, IEEE Transactions on Circuits and Systems II: Express Briefs, vol.54, issue.11, pp.974-978, 2007.
DOI : 10.1109/TCSII.2007.903212

J. Muller, N. Brisebarre, F. De-dinechin, C. Jeannerod, V. Lefèvre et al., Handbook of Floating-Point Arithmetic, 2009.
DOI : 10.1007/978-0-8176-4705-6
URL : https://hal.archives-ouvertes.fr/ensl-00379167