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Poster communications

Accurate Modeling of Fault Impact in Arithmetic Circuits

Abstract : Various methods have been proposed for fault detection and fault tolerance in digital integrated circuits. In the case of arithmetic circuits, the selection of an efficient method depends on several elements: type of operation, type(s) of operand(s), computation algorithms, internal representations of numbers, optimizations at architecture and circuit levels, and acceptable accuracy level (i.e. mathematical error) of the result(s) including both rounding errors and errors due to the faults. High-level mathematical models are not sufficient to capture the effect of faults in arithmetic circuits. Simulation of intensive fault scenarios in all components of the arithmetic circuit (data-path, control, gates with important fan-out such as some partial products generation in large multipliers, etc.) is widely used. But cycle accurate and bit accurate software simulations at gate level are too slow for large circuits and numerous fault scenarios. FPGA emulation is a popular method to speed-up fault simulation. In the demo, we will present an hardware-software platform dedicated to fault emulation for ASIC arithmetic circuits. The platform is based on a parallel cluster of Zynq FPGA cards and a Linux server. Various arithmetic circuits and fault models will be demonstrated in the context of digital signal and image processing.
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https://hal.inria.fr/hal-01404772
Contributor : Arnaud Tisserand <>
Submitted on : Tuesday, November 29, 2016 - 11:29:34 AM
Last modification on : Friday, July 10, 2020 - 4:11:17 PM
Document(s) archivé(s) le : Monday, March 20, 2017 - 9:35:31 PM

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poster-dasip-demo-night.pdf
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  • HAL Id : hal-01404772, version 1

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Pierre Guilloux, Arnaud Tisserand. Accurate Modeling of Fault Impact in Arithmetic Circuits. DASIP: Conference on Design and Architectures for Signal and Image Processing (Demo Night), Oct 2016, Rennes, France. 2016. ⟨hal-01404772⟩

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