Dark Silicon and the End of Multicore Scaling, 38th Annual International Symposium on Computer ArchitectureISCA), pp.365-376, 2011. ,
Wattch: a framework for architectural-level power analysis and optimizations, 27th International Symposium on Computer Architecture (ISCA), pp.83-94, 2000. ,
DOI : 10.1109/isca.2000.854380
URL : http://american.cs.ucdavis.edu/academic/readings/papers/architecturepoweranalysis.pdf
McPAT, Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, Micro-42, pp.469-480, 2009. ,
DOI : 10.1145/1669112.1669172
The M5 Simulator: Modeling Networked Systems, IEEE Micro, vol.26, issue.4, pp.52-60, 2006. ,
DOI : 10.1109/MM.2006.82
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset, ACM SIGARCH Computer Architecture News, vol.33, issue.4, pp.92-99, 2005. ,
DOI : 10.1145/1105734.1105747
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.109.5362
The gem5 simulator, ACM SIGARCH Computer Architecture News, vol.39, issue.2, pp.1-7, 2011. ,
DOI : 10.1145/2024716.2024718
Instruction level power analysis and optimization of software, 9th International Conference on VLSI Design (VLSI), pp.326-328, 1996. ,
DOI : 10.1007/978-1-4613-1453-0_9
Functional level power analysis: an efficient approach for modeling the power consumption of complex processors, Proceedings Design, Automation and Test in Europe Conference and Exhibition, pp.1-6, 2004. ,
DOI : 10.1109/DATE.2004.1268921
URL : https://hal.archives-ouvertes.fr/hal-00013979
ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration, 2009 Design, Automation & Test in Europe Conference & Exhibition, pp.423-428, 2009. ,
DOI : 10.1109/DATE.2009.5090700
VPPET: Virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms, 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp.1-8, 2014. ,
DOI : 10.1109/PATMOS.2014.6951910
A clustered manycore processor architecture for embedded and accelerated applications, 2013 IEEE High Performance Extreme Computing Conference (HPEC), pp.1-6, 2013. ,
DOI : 10.1109/HPEC.2013.6670342
TILE-Gx100 ManyCore processor: Acceleration interfaces and architecture, 2011 IEEE Hot Chips 23 Symposium (HCS), 2011. ,
DOI : 10.1109/HOTCHIPS.2011.7477491
GeCoS: A framework for prototyping custom hardware design flows, 2013 IEEE 13th International Working Conference on Source Code Analysis and Manipulation (SCAM), pp.100-105, 2013. ,
DOI : 10.1109/SCAM.2013.6648190
URL : https://hal.archives-ouvertes.fr/hal-00921370
MAPS, Proceedings of the 45th annual conference on Design automation, DAC '08, pp.754-759, 2008. ,
DOI : 10.1145/1391469.1391663