Simulating MPI applications: the SMPI approach

Augustin Degomme 1 Arnaud Legrand 2 Mark Markomanolis 3 Martin Quinson 4 Mark Stillwell 5 Frédéric Suter 6, 7
1 Unibas - University of Basel
2 POLARIS - Performance analysis and optimization of LARge Infrastructures and Systems
Inria Grenoble - Rhône-Alpes, LIG - Laboratoire d'Informatique de Grenoble
3 KAUST - King Abdullah University of Science and Technology
4 MYRIADS - Design and Implementation of Autonomous Distributed Systems
Inria Rennes – Bretagne Atlantique , IRISA_D1 - SYSTÈMES LARGE ÉCHELLE
5 Imperial College London
6 AVALON - Algorithms and Software Architectures for Distributed and HPC Platforms
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
7 CC-IN2P3 - Centre de Calcul de l'IN2P3
Abstract : This article summarizes our recent work and developments on SMPI, a flexible simulator of MPI applications. In this tool, we took a particular care to ensure our simulator could be used to produce fast and accurate predictions in a wide variety of situations. Although we did build SMPI on SimGrid whose speed and accuracy had already been assessed in other contexts, moving such techniques to a HPC workload required significant additional effort. Obviously, an accurate modeling of communications and network topology was one of the key to such achievements. Another less obvious key was the choice to combine in a single tool the possibility to do both offline and online simulation.
Keywords : Simulation MPI runtime and applications Performance prediction and extrapolation
Type de document :
Article dans une revue
IEEE Transactions on Parallel and Distributed Systems, Institute of Electrical and Electronics Engineers, 2017, pp.14. <10.1109/TPDS.2017.2669305>
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Soumis le : mercredi 3 mai 2017 - 11:00:32
Dernière modification le : jeudi 15 juin 2017 - 09:08:55

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Augustin Degomme, Arnaud Legrand, Mark Markomanolis, Martin Quinson, Mark Stillwell, et al.. Simulating MPI applications: the SMPI approach. IEEE Transactions on Parallel and Distributed Systems, Institute of Electrical and Electronics Engineers, 2017, pp.14. <10.1109/TPDS.2017.2669305>. <hal-01415484v2>

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