A static analysis for the minimization of voters in fault-tolerant circuits

Abstract : We present a formal approach to minimize the number of voters in triple-modular redundant (TMR) sequential circuits. Our technique actually works on a single copy of the TMR circuit and considers a large class of fault models of the form ``at most 1 SEU or SET every k clock cycles''. Verification-based voter minimization guarantees that the resulting TMR circuit (i) is fault tolerant to the soft-errors defined by the fault model and (ii) is functionally equivalent to the initial TMR circuit. Our approach operates at the logic level and takes into account the input and output interface specifications of the circuit. Its implementation makes use of graph traversal algorithms, fixed-point iterations, and binary decision diagrams (BDD). Experimental results on the ITC'99 benchmark suite indicate that our method significantly decreases the number of inserted voters, yielding a hardware reduction of up to 55% and a clock frequency increase of up to35% compared to full TMR.
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[Research Report] RR-9004, Inria - Research Centre Grenoble – Rhône-Alpes. 2016, pp.1-27
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https://hal.inria.fr/hal-01417164
Contributeur : Pascal Fradet <>
Soumis le : jeudi 15 décembre 2016 - 12:47:41
Dernière modification le : mardi 20 décembre 2016 - 11:09:56
Document(s) archivé(s) le : jeudi 16 mars 2017 - 18:44:34

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Dmitry Burlyaev, Pascal Fradet, Alain Girault. A static analysis for the minimization of voters in fault-tolerant circuits. [Research Report] RR-9004, Inria - Research Centre Grenoble – Rhône-Alpes. 2016, pp.1-27. <hal-01417164>

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