M. Aagaard, R. Jones, and C. Seger, Formal verication using parametric representations of boolean constraints, Design Automation Conference (DAC), p.402407, 1999.
DOI : 10.1109/dac.1999.781349

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.409.8282

B. B. Alagoz, Fault masking by probabilistic voting. OncuBilim Algorithm And Systems Labs, 2009.

S. Baarir and C. Braunstein, Complementary Formal Approaches for Dependability Analysis, 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
DOI : 10.1109/DFT.2009.21

URL : https://hal.archives-ouvertes.fr/hal-00469821

I. In and . Int, Symp. on Defect and Fault Tolerance in VLSI Systems, p.331339, 2009.

S. Baarir, Feasibility analysis for MEU robustness quantication by symbolic model checking, Proceedings in Formal Methods of Software Design, 2011.
DOI : 10.1007/s10703-011-0121-5

A. Bogorad, On-Orbit Error Rates of RHBD SRAMs: Comparison of Calculation Techniques and Space Environmental Models With Observed Performance, IEEE Transactions on Nuclear Science, vol.58, issue.6, p.28042806, 2011.
DOI : 10.1109/TNS.2011.2167242

B. Bridgford, C. Carmichael, and C. W. Tseng, Single-event upset mitigation selection guide, Xilinx Application Note XAPP987, vol.1, 2008.

P. Brinkley, P. Avnet, and C. Carmichael, SEU mitigation design techniques for the XQR4000XL, 2000.

S. P. Buchner and M. P. Baze, Single-event transients in fast electronic circuits, IEEE NSREC Short Course, p.1105, 2001.

D. Burlyaev, Design, optimization, and formal verication of circuit fault-tolerance techniques, 2015.

D. Burlyaev, P. Fradet, and A. Girault, Verication-guided voter minimization in triplemodular redundant circuits, Design, Automation & Test in Europe Conference & Exhibition, p.16, 2014.
DOI : 10.7873/date.2014.105

D. Burlyaev, P. Fradet, and A. Girault, Automatic Time-Redundancy Transformation for Fault-Tolerant Circuits, Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '15, p.218227, 2015.
DOI : 10.1145/2684746.2689058

URL : https://hal.archives-ouvertes.fr/hal-01095747

]. D. Burlyaev, P. Fradet, and A. Girault, Time-redundancy transformations for adaptive faulttolerant circuits, NASA/ESA Conference on Adaptive Hardware and Systems (AHS), p.18, 2015.
DOI : 10.1109/ahs.2015.7231164

URL : https://hal.archives-ouvertes.fr/hal-01253111

G. Cabodi and S. Singh, Complete and Eective Robustness Checking by Means of Interpolation, Formal Methods in Computer-Aided Design, p.2012

A. C. Chiang, I. S. Reed, and A. V. Banes, Path sensitization, partial boolean dierence, and automated fault diagnosis, IEEE Trans. Computers, vol.21, issue.2, p.189195, 1972.
DOI : 10.1109/tc.1972.5008925

E. M. Clarke, J. R. Burch, O. Grumberg, D. E. Long, and K. L. Mcmillan, Mechanized reasoning and hardware design. chapter Automatic Verication of Sequential Circuit Designs, p.105120, 1992.

F. Corno, M. Reorda, and G. Squillero, RT-level ITC'99 benchmarks and rst ATPG results, Design Test of Computers, p.4453, 2000.
DOI : 10.1109/54.867894

G. and D. Micheli, Synthesis and Optimization of Digital Circuits. McGraw-Hill Higher Education, 1994.

D. E. Denning and P. J. Denning, Certication of programs for secure information ow, Commun. ACM, vol.20, issue.7, p.504513, 1977.

R. D. Do, New tool for FPGA designers mitigates soft errors within synthesis, 2011.

P. Dodd, M. Shaneyfelt, J. Schwank, and G. Hash, Neutron-induced soft errors, latchup, and comparison of SER test methods for SRAM technologies, Digest. International Electron Devices Meeting,, p.333336, 2002.
DOI : 10.1109/IEDM.2002.1175846

G. Even, J. S. Naor, B. Schieber, and M. Sudan, Approximating minimum feedback sets and multi-cuts in directed graphs, Proc. 4th Int. Conf. on Int. Prog. and Combinatorial Opt, p.1428, 1995.
DOI : 10.1007/3-540-59408-6_38

G. Fey, A. Sülow, and R. Drechsler, Computing bounds for fault tolerance using formal techniques, Proceedings of the 46th Annual Design Automation Conference on ZZZ, DAC '09, p.190195, 2009.
DOI : 10.1145/1629911.1629963

S. Habinc, Functional triple modular redundancy FTMR, European Space Agency Contract Report, 2002.

K. Hass and J. Ambles, Single event transients in deep submicron CMOS, 42nd Midwest Symposium on Circuits and Systems (Cat. No.99CH36356), p.122125, 1999.
DOI : 10.1109/MWSCAS.1999.867224

J. P. Hayes, I. Polian, and B. Becker, An Analysis Framework for Transient-Error Tolerance, 25th IEEE VLSI Test Symmposium (VTS'07), pp.6-10, 2007.
DOI : 10.1109/VTS.2007.13

T. Heijmen, Soft-error vulnerability of sub-100-nm ip-ops, 14th IEEE Int.On-Line Testing Symposium, p.247252, 2008.
DOI : 10.1109/iolts.2008.12

T. Imagawa, H. Tsutsui, H. Ochi, and T. Sato, A cost-eective selective tmr for heterogeneous coarse-grained recongurable architectures based on dfg-level vulnerability analysis, 2013 Design, Automation Test in Europe Conference Exhibition (DATE), p.701706, 2013.

J. M. Johnson and M. J. Wirthlin, Voter insertion algorithms for FPGA designs using triple modular redundancy, Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays, FPGA '10, p.249258, 2010.
DOI : 10.1145/1723112.1723154

R. Karp, Reducibility among combinatorial problems, Complexity of Computer Computations, vol.43, p.85103, 1972.
DOI : 10.1007/978-3-540-68279-0_8

S. Kilts, Advanced FPGA Design: Architecture, Implementation, and Optimization, 2007.
DOI : 10.1002/9780470127896

H. T. Nguyen and Y. , A systematic approach to SER estimation and solutions, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual., p.6070, 2003.
DOI : 10.1109/RELPHY.2003.1197722

I. Polian, B. Becker, M. Nakasato, S. Ohtake, and H. Fujiwara, Low-Cost Hardening of Image Processing Applications Against Soft Errors, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp.4-6, 2006.
DOI : 10.1109/DFT.2006.40

B. Pratt, M. Carey, P. Graham, K. Morgan, and M. Wirthlin, Improving FPGA Design Robustness with Partial TMR, 2006 IEEE International Reliability Physics Symposium Proceedings, p.226232, 2006.
DOI : 10.1109/RELPHY.2006.251221

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.125.6067

O. Ruano, P. Reviriego, and J. Maestro, Automatic insertion of selective TMR for SEU mitigation, 2008 European Conference on Radiation and Its Effects on Components and Systems, pp.284-287, 2008.
DOI : 10.1109/RADECS.2008.5782728

P. Samudrala, Selective triple Modular redundancy (STMR) based single-event upset (SEU) tolerant synthesis for FPGAs, IEEE Transactions on Nuclear Science, vol.51, issue.5, pp.284-287, 2004.
DOI : 10.1109/TNS.2004.834955

S. Seshia, W. Li, and S. Mitra, Verication-guided soft error resilience, DATE '07, p.16, 2007.
DOI : 10.1109/date.2007.364501

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.86.483

P. Shivakumar, M. Kistler, S. Keckler, D. Burger, and L. Alvisi, Modeling the eect of technology trends on the soft error rate of combinational logic, Dependable Systems and Networks Proceedings. International Conference on, p.389398, 2002.

A. Sutton, Creating highly reliable FPGA designs, Military&Aerospace Technical Bullentin, Issue, vol.1, p.57, 2013.

J. Neumann, Probabilistic Logics and the Synthesis of Reliable Organisms From Unreliable Components, Automata Studies, p.4398, 1956.
DOI : 10.1515/9781400882618-003

J. Ziegler, IBM experiments in soft fails in computer electronics, IBM Journal of Research and Development, vol.40, issue.1, p.318, 1978.
DOI : 10.1147/rd.401.0003

R. N°-9004 and R. Centre-grenoble-?-rhône-alpes, Inovallée 655 avenue de l'Europe Montbonnot 38334 Saint Ismier Cedex Publisher Inria Domaine de Voluceau -Rocquencourt BP 105 -78153 Le Chesnay Cedex inria, pp.249-6399