Hardware-Accelerated Dynamic Binary Translation

Simon Rokicki 1 Erven Rohou 2 Steven Derrien 1
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA_D3 - ARCHITECTURE
2 PACAP - Pushing Architecture and Compilation for Application Performance
Inria Rennes – Bretagne Atlantique , IRISA_D3 - ARCHITECTURE
Abstract : Dynamic Binary Translation (DBT) is often used in hardware/software co-design to take advantage of an architecture model while using binaries from another one. The co-development of the DBT engine and of the execution architecture leads to architecture with special support to these mechanisms. In this work, we propose a hardware accelerated Dynamic Binary Translation where the first steps of the DBT process are fully accelerated in hardware. Results shows that using our hardware accelerators leads to a speed-up of 8× and a cost in energy 18× lower, compared with an equivalent software approach.
Type de document :
Communication dans un congrès
IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2017, Lausanne, Switzerland. IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 〈https://www.date-conference.com/〉
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Soumis le : lundi 3 avril 2017 - 10:39:45
Dernière modification le : jeudi 11 janvier 2018 - 06:28:14
Document(s) archivé(s) le : mardi 4 juillet 2017 - 12:39:54

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Simon Rokicki, Erven Rohou, Steven Derrien. Hardware-Accelerated Dynamic Binary Translation. IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar 2017, Lausanne, Switzerland. IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 〈https://www.date-conference.com/〉. 〈hal-01423639〉

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