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Towards Scalable and Efficient FPGA Stencil Accelerators

Gaël Deest 1 Nicolas Estibals 1 Tomofumi Yuki 2 Steven Derrien 1 Sanjay Rajopadhye 3 
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
2 COMPSYS - Compilation and embedded computing systems
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : In this paper we propose a design template for stencil computations targeting FPGA-based accelerators. The goal for our design is to provide scalable high throughput designs that can efficiently process iterative stencil programs with large size parameters, i.e., those whose data footprint is too large to fit on-chip. Our context is when we seek to use FP-GAs as accelerators attached to CPUs. Minimizing the area is not our primary goal. We propose a family of architectures based on hierarchical tiling, where the inner tiling is used to build coarse-grain data-path operators, increasing computational throughput, and the outer tiling is used to control the memory requirement , specifically data transfers to/from the accelerator. We present preliminary results for Jacobi-style stencils on 1D and 2D data, and are working on fully automating the flow.
Keywords : stencils accelerators
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Conference papers
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Contributor : Gaël Deest Connect in order to contact the contributor
Submitted on : Tuesday, January 3, 2017 - 11:27:17 AM
Last modification on : Friday, November 18, 2022 - 9:26:27 AM
Long-term archiving on: : Tuesday, April 4, 2017 - 1:07:14 PM


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  • HAL Id : hal-01425018, version 1



Gaël Deest, Nicolas Estibals, Tomofumi Yuki, Steven Derrien, Sanjay Rajopadhye. Towards Scalable and Efficient FPGA Stencil Accelerators. IMPACT'16 - 6th International Workshop on Polyhedral Compilation Techniques, held with HIPEAC'16, Jan 2016, Prague, Czech Republic. ⟨hal-01425018⟩



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