Superword Level Parallelism aware Word Length Optimization

Abstract : Many embedded processors do not support floating-point arithmetic in order to comply with strict cost and power consumption constraints. But, they generally provide support for SIMD as a mean to improve performance for little cost overhead. Achieving good performance when targeting such processors requires the use of fixed-point arithmetic and efficient exploitation of SIMD data-path. To reduce time-to-market, automatic SIMDization – such as superword level parallelism (SLP) extraction – and float-to-fixed-point conversion methodologies have been proposed. In this paper we show that applying these transformations independently is not efficient. We propose a SLP-aware word length optimization algorithm to jointly perform float-to-fixed-point conversion and SLP extraction. We implement the proposed approach in a source-to-source compiler framework and evaluate it on several embedded processors. Experimental results illustrate the validity of our approach.
Type de document :
Communication dans un congrès
David Atienza; Giorgio Di Natale. Design, Automation & Test in Europe Conference & Exhibition (DATE 2017), Mar 2017, Lausanne, Switzerland. IEEE, 2017, 〈https://www.date-conference.com/〉
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https://hal.inria.fr/hal-01425550
Contributeur : Ali Hassan El Moussawi <>
Soumis le : mardi 3 janvier 2017 - 17:15:15
Dernière modification le : mercredi 16 mai 2018 - 11:24:13
Document(s) archivé(s) le : mardi 4 avril 2017 - 14:36:26

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  • HAL Id : hal-01425550, version 1

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Ali Hassan El Moussawi, Steven Derrien. Superword Level Parallelism aware Word Length Optimization. David Atienza; Giorgio Di Natale. Design, Automation & Test in Europe Conference & Exhibition (DATE 2017), Mar 2017, Lausanne, Switzerland. IEEE, 2017, 〈https://www.date-conference.com/〉. 〈hal-01425550〉

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