Relaxing Synchronization in a Parallel SystemC Kernel

Abstract : SystemC has become a very popular standardized language for the modeling of system-on-chip (SoC) devices. However, due to the ever increasing complexity of SoC designs, the ever longer simulation times affect SoC exploration potential and time-to-market. In order to reduce these times, we have developed a parallel SystemC kernel. Because the SystemC semantics require a high level of synchronization which can dramatically affect the performance gains, we investigate in this paper some ways to reduce the synchronization overheads. We validate then our approaches against an academic design model and a real, industrial application.
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Communication dans un congrès
IEEE Computer Society. ISPA 2008 - International Symposium on Parallel and Distributed Processing with Applications, Dec 2008, Sydney, Australia. IEEE, 2008 IEEE International Symposium on Parallel and Distributed Processing with Applications, pp.180-187, 〈10.1109/ISPA.2008.124〉
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https://hal.inria.fr/hal-01428323
Contributeur : Eddy Caron <>
Soumis le : vendredi 6 janvier 2017 - 13:20:26
Dernière modification le : lundi 12 novembre 2018 - 10:57:28

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Philippe Combes, Eddy Caron, Frédéric Desprez, Bastien Chopard, Julien Zory. Relaxing Synchronization in a Parallel SystemC Kernel. IEEE Computer Society. ISPA 2008 - International Symposium on Parallel and Distributed Processing with Applications, Dec 2008, Sydney, Australia. IEEE, 2008 IEEE International Symposium on Parallel and Distributed Processing with Applications, pp.180-187, 〈10.1109/ISPA.2008.124〉. 〈hal-01428323〉

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