SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture

Abstract : Electric devices should be resilient because reliability issues are increasingly problematic as technology scales down and the supply voltage is lowered. Specifically, the Soft-Error Rate (SER) increases due to the reduced feature size and the reduced charge. This paper describes an adaptive method to lower memory power using a dual Vdd in a column-based Vdd memory with Built-In Current Sensors (BICS). Using our method, we reduce the memory power by about 40% and increase the error immunity of the memory without the significant power overhead as in previous methods.
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Communication dans un congrès
Andreas Burg; Ayse Coskun; Matthew Guthaus; Srinivas Katkoori; Ricardo Reis. 20th International Conference on Very Large Scale Integration (VLSI-SoC), Aug 2012, Santa Cruz, CA, United States. Springer, IFIP Advances in Information and Communication Technology, AICT-418, pp.181-195, 2013, VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design. 〈10.1007/978-3-642-45073-0_10〉
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Seokjoong Kim, Matthew Guthaus. SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture. Andreas Burg; Ayse Coskun; Matthew Guthaus; Srinivas Katkoori; Ricardo Reis. 20th International Conference on Very Large Scale Integration (VLSI-SoC), Aug 2012, Santa Cruz, CA, United States. Springer, IFIP Advances in Information and Communication Technology, AICT-418, pp.181-195, 2013, VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design. 〈10.1007/978-3-642-45073-0_10〉. 〈hal-01456956〉

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