K. Bhattacharya and N. Ranganathan, RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits, 2009 22nd International Conference on VLSI Design, pp.453-458, 2009.
DOI : 10.1109/VLSI.Design.2009.76

L. Ding and P. Mazumder, Dynamic noise margin: definitions and model, 17th International Conference on VLSI Design. Proceedings., pp.1001-1006, 2004.
DOI : 10.1109/ICVD.2004.1261061

L. B. Freeman, Critical charge calculations for a bipolar SRAM array, IBM Journal of Research and Development, vol.40, issue.1, pp.119-129, 1996.
DOI : 10.1147/rd.401.0119

R. W. Hamming, Error Detecting and Error Correcting Codes, Bell System Technical Journal, vol.29, issue.2, pp.147-160, 1950.
DOI : 10.1002/j.1538-7305.1950.tb00463.x
URL : http://campus.unibo.it/10913/1/hamming1950.pdf

F. Hamzaoglu and Y. Wang, Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design, IEEE Design & Test of Computers, vol.28, issue.1, pp.22-31, 2011.
DOI : 10.1109/MDT.2011.5

P. Hazucha and C. Svensson, Impact of CMOS technology scaling on the atmospheric neutron soft error rate, IEEE Transactions on Nuclear Science, vol.47, issue.6, pp.2586-2594, 2000.
DOI : 10.1109/23.903813

G. Huang and W. Dong, Tracing SRAM separatrix for dynamic noise margin analysis under device mismatch, 2007 IEEE International Behavioral Modeling and Simulation Workshop, pp.6-10, 2007.
DOI : 10.1109/BMAS.2007.4437516

S. Kim and M. Guthaus, Leakage-aware redundancy for reliable sub-threshold memories, Proceedings of the 48th Design Automation Conference on, DAC '11, pp.435-440, 2011.
DOI : 10.1145/2024724.2024826

S. Kim and M. Guthaus, Low-power multiple-bit upset tolerant memory optimization, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp.577-581, 2011.
DOI : 10.1109/ICCAD.2011.6105388

S. Kim and M. Guthaus, SNM-aware power reduction and reliability improvement in 45nm SRAMs, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, pp.204-207, 2011.
DOI : 10.1109/VLSISoC.2011.6081666

A. Lesea and S. Drimer, The rosetta experiment: atmospheric soft error rate testing in differing technology FPGAs, IEEE Transactions on Device and Materials Reliability, vol.5, issue.3, pp.317-328, 2005.
DOI : 10.1109/TDMR.2005.854207

S. Michalak and K. Harris, Predicting the number of fatal soft errors in Los Alamos national laboratory's ASC Q supercomputer, IEEE Transactions on Device and Materials Reliability, vol.5, issue.3, pp.329-335, 2005.
DOI : 10.1109/TDMR.2005.855685

P. C. Murley and G. R. Srinivasan, Soft-error Monte Carlo modeling program, SEMM, IBM Journal of Research and Development, vol.40, issue.1, pp.109-118, 1996.
DOI : 10.1147/rd.401.0109

E. Neto and I. Ribeiro, Using Bulk Built-in Current Sensors to Detect Soft Errors, IEEE Micro, vol.26, issue.5, pp.10-18, 2006.
DOI : 10.1109/MM.2006.103

E. Normand, Single event upset at ground level, IEEE Transactions on Nuclear Science, vol.43, issue.6, pp.2742-2750, 1996.
DOI : 10.1109/23.556861

A. Pavlov and M. Sachdev, CMOS SRAM circuit design and parametric test in nano-scaled technologies: process-aware SRAM design, 2008.
DOI : 10.1007/978-1-4020-8363-1

R. Rajaraman and J. S. Kim, SEAT-LA: a soft error analysis tool for combinational logic, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006.
DOI : 10.1109/VLSID.2006.143
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.123.868

P. Reviriego and J. A. Maestro, Reliability analysis of memories protected with BICS and a per-word parity bit, ACM Transactions on Design Automation of Electronic Systems, vol.15, issue.2, pp.1-1815, 2010.
DOI : 10.1145/1698759.1698768

P. Shivakumar and M. Kistler, Modeling the effect of technology trends on the soft error rate of combinational logic, Proceedings International Conference on Dependable Systems and Networks, pp.389-398, 2002.
DOI : 10.1109/DSN.2002.1028924

F. Vargas and M. Nicolaidis, SEU-tolerant SRAM design based on current monitoring, Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing, pp.106-115, 1994.
DOI : 10.1109/FTCS.1994.315652
URL : https://hal.archives-ouvertes.fr/hal-00013937

E. Vatajelu, A. Go, and . Pau, Transient Noise Failures in SRAM Cells: Dynamic Noise Margin Metric, 2011 Asian Test Symposium, pp.413-418, 2011.
DOI : 10.1109/ATS.2011.64

J. Wang, S. Nalam, and B. Calhoun, Analyzing static and dynamic write margin for nanometer SRAMs, Proceeding of the thirteenth international symposium on Low power electronics and design, ISLPED '08, pp.129-134, 2008.
DOI : 10.1145/1393921.1393954
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.562.6481

F. Yang and C. Huang, 45nm node planar-SOI technology with 0.296 µm 2 6T- SRAM cell, VLSI Technology Digest of Technical Papers. 2004 Symposium on, pp.8-9, 2004.

B. Zhang and A. Arapostathis, Analytical modeling of SRAM dynamic stability, IEEE/ACM International Conference on, pp.315-322, 2006.

K. Zhang and U. Bhattacharya, A 3-ghz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply. Solid-State Circuits, IEEE Journal, vol.51, issue.1, pp.146-151, 2006.

M. Zhang and N. Shanbhag, Soft-error-rate-analysis (SERA) methodology. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.25, issue.10, pp.2140-2155, 2006.
DOI : 10.1109/tcad.2005.862738

J. F. Ziegler, Terrestrial cosmic rays, IBM Journal of Research and Development, vol.40, issue.1, pp.19-39, 1996.
DOI : 10.1147/rd.401.0019

J. F. Ziegler and W. A. Lanford, Effect of Cosmic Rays on Computer Memories, Science, vol.206, issue.4420, pp.776-788, 1979.
DOI : 10.1126/science.206.4420.776