A Smart Memory Accelerated Computed Tomography Parallel Backprojection

Abstract : As nanoscale lithography challenges mandate greater pattern regularity and commonality for logic and memory circuits, new opportunities are created to affordably synthesize more powerful smart memory blocks for specific applications. Leveraging the ability to embed logic inside the memory block boundary, we demonstrate the synthesis of smart memory architectures that exploits the inherent memory address patterns of the backprojection algorithm to enable efficient parallel image reconstruction at minimum hardware overhead. An end-to-end design framework in sub-20nm CMOS technologies was constructed for the physical synthesis of smart memories and evaluation of the huge design space. Our experimental results show that customizing memory for the computerized tomography (CT) parallel backprojection can achieve more than 30% area and power savings while offering significant performance improvements with marginal sacrifice of image accuracy.
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Communication dans un congrès
Andreas Burg; Ayse Coskun; Matthew Guthaus; Srinivas Katkoori; Ricardo Reis. 20th International Conference on Very Large Scale Integration (VLSI-SoC), Aug 2012, Santa Cruz, CA, United States. Springer, IFIP Advances in Information and Communication Technology, AICT-418, pp.21-44, 2013, VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design. 〈10.1007/978-3-642-45073-0_2〉
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Qiuling Zhu, Larry Pileggi, Franz Franchettis. A Smart Memory Accelerated Computed Tomography Parallel Backprojection. Andreas Burg; Ayse Coskun; Matthew Guthaus; Srinivas Katkoori; Ricardo Reis. 20th International Conference on Very Large Scale Integration (VLSI-SoC), Aug 2012, Santa Cruz, CA, United States. Springer, IFIP Advances in Information and Communication Technology, AICT-418, pp.21-44, 2013, VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design. 〈10.1007/978-3-642-45073-0_2〉. 〈hal-01456960〉

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