M. Psarakis, D. Gizopoulos, E. Sanchez, and M. S. Reorda, Microprocessor softwarebased self-testing, IEEE Design & Test of Computers, vol.2, issue.3, pp.4-19, 2010.
DOI : 10.1109/mdt.2010.5

P. Bernardi, E. Sànchez, M. Schillaci, G. Squillero, and M. S. Reorda, An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs, Europe, DATE '06, pp.1-6, 2006.

L. Chen and S. Dey, Software-based diagnosis for processors, Proceedings of the 39th conference on Design automation , DAC '02, pp.259-262, 2002.
DOI : 10.1145/513918.513986

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.11.9253

J. A. Fisher, P. Faraboschi, and C. Young, Embedded computing: a VLIW approach to architecture , compilers and tools, 2004.

B. Bornstein, T. Estlin, B. Clement, and P. Springer, Using a multicore processor for rover autonomous science, 2011 Aerospace Conference, pp.1-9, 2011.
DOI : 10.1109/AERO.2011.5747454

T. Corporation, Multicore Development Environment User Guide, Doc #UG201 Release 1.2, 2008.

M. Beardo, F. Bruschi, F. Ferrandi, and D. Sciuto, An approach to functional testing of VLIW architectures, Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786), pp.29-33, 2000.
DOI : 10.1109/HLDVT.2000.889555

D. Sabena, M. Sonza-reorda, and L. Sterpone, A new SBST algorithm for testing the register file of VLIW processors, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.412-417, 2012.
DOI : 10.1109/DATE.2012.6176506

M. Ulbricht, M. Schölzer, T. Koal, and H. T. Vierhaus, A new hierarchical built-in self-test with on-chip diagnosis for VLIW processors, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, pp.143-146, 2011.
DOI : 10.1109/DDECS.2011.5783067

S. Wong, F. Anjam, and F. Nadeem, Dynamically reconfigurable register file for a softcore VLIW processor, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), pp.962-972, 2010.
DOI : 10.1109/DATE.2010.5456908

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.658.9245

S. Wong, T. Van-as, and G. Brown, ?-VEX: a reconfigurable and extensible softcore VLIW processor, International Conference on ICECE Technology, pp.369-372, 2010.

N. Kranitis, A. Paschalis, D. Gizopoulos, and G. Xenoulis, Software-Based Self-Testing of Embedded Processors, IEEE Transactions on Computers, vol.54, issue.4, pp.461-475, 2005.
DOI : 10.1109/TC.2005.68

T. Koal and H. T. Vierhaus, A software-based self-test and hardware reconfiguration solution for VLIW processors, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, pp.40-43, 2010.
DOI : 10.1109/DDECS.2010.5491821

M. Ulbricht, M. Scholzel, T. Koal, and H. T. Vierhaus, A new hierarchical built-in selftest with on-chip diagnosis for VLIW processors, IEEE Symposium on Design and Diagnostic of Electronic Circuits and Systems (DDECS), pp.143-146, 2011.

A. Pillai, W. Zhang, and D. Kagaris, Detecting VLIW Hard Errors Cost-Effectively through a Software-Based Approach, 21st International Conference on Advanced Information Networking and Applications Workshops (AINAW'07), pp.811-815, 2007.
DOI : 10.1109/AINAW.2007.152

D. Gizopoulos, M. Psarakis, M. Hatzimihail, M. Maniatakos, A. Paschalis et al., Systematic Software-Based Self-Test for Pipelined Processors, IEEE Transaction on Very Large Scale Integration (VLSI) Systems, pp.1441-1453, 2008.
DOI : 10.1109/TVLSI.2008.2000866

A. Paschalis, D. Gizopoulos, N. Kranitis, M. Psarakis, and Y. Zorian, Deterministic software-based self-testing of embedded processor cores, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, pp.92-96, 2001.
DOI : 10.1109/DATE.2001.915006

N. Kranitis, D. Gizopoulos, A. Paschalis, and M. Psarakis, Instruction-based self-testing of processor cores, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), pp.223-228, 2002.
DOI : 10.1109/VTS.2002.1011142

E. Sanchez, M. Sonza-reorda, and G. Squillero, On the transformation of manufacturing test sets into on-line test sets for microprocessors, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), pp.494-502, 2005.
DOI : 10.1109/DFTVS.2005.53

P. Bernardi, E. Sánchez, M. Schillaci, G. Squillero, and M. S. Reorda, An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.27, issue.3, pp.27-570, 2008.
DOI : 10.1109/TCAD.2008.915541

M. Koester, W. S. Luk, J. Hagemeyer, M. Porrmann, and U. Rückert, Design Optimizations for Tiled Partially Reconfigurable Systems Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.19, issue.6, pp.1048-1061, 2011.
DOI : 10.1109/tvlsi.2010.2044902

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.310.3014

P. G. Ryan, Fault dictionary compression and equivalence class computation for sequential circuits, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD), pp.508-511, 1993.
DOI : 10.1109/ICCAD.1993.580105