A. Radio and I. , Arinc 653: Avionics application software standard interface, 2003.

M. Fakih, K. Grüttner, M. Fränzle, and A. Rettberg, Towards Performance Analysis of SDFGs Mapped to Shared-Bus Architectures Using Model-Checking, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 2013.
DOI : 10.7873/DATE.2013.243

S. Sriram and S. S. Bhattacharyya, Embedded Multiprocessors: Scheduling and Synchronization . 1 edn, 2000.
DOI : 10.1201/9781420048025

M. Lv, W. Yi, N. Guan, and G. Yu, Combining Abstract Interpretation with Model Checking for Timing Analysis of Multicore Software, 2010 31st IEEE Real-Time Systems Symposium, pp.339-349, 2010.
DOI : 10.1109/RTSS.2010.30

G. Giannopoulou, K. Lampka, N. Stoimenov, and L. Thiele, Timed model checking with abstractions, Proceedings of the tenth ACM international conference on Embedded software, EMSOFT '12, pp.63-72, 2012.
DOI : 10.1145/2380356.2380372

C. Dong-il, C. Hyung, and M. Jan, System-Level Verification of Multi-Core Embedded Systems Using Timed-Automata, pp.9302-9307, 2008.

A. Ghamarian, Timing Analysis of Synchronous Data Flow Graphs, 2008.

A. Moonen, Predictable Embedded Multiprocessor Architecture for Streaming Applications, 2009.

A. Kumar, Analysis, Design and Management of Multimedia Multiprocessor Systems, 2009.

Y. Yang, M. Geilen, T. Basten, S. Stuijk, and H. Corporaal, Automated bottleneckdriven design-space exploration of media processing systems, Proceedings of the Conference on Design, Automation and Test in Europe. DATE '10, pp.1041-1046, 2010.

A. Shabbir, A. Kumar, S. Stuijk, B. Mesman, and H. Corporaal, CA-MPSoC: An automated design flow for predictable multi-processor architectures for multiple applications, Journal of Systems Architecture, vol.56, issue.7, pp.265-277, 2010.
DOI : 10.1016/j.sysarc.2010.03.007

A. Kumar, B. Mesman, B. Theelen, H. Corporaal, and Y. Ha, Analyzing composability of applications on MPSoC platforms, Journal of Systems Architecture, vol.54, issue.3-4, pp.3-4, 2008.
DOI : 10.1016/j.sysarc.2007.10.002

A. Gerstlauer, C. Haubelt, A. Pimentel, T. Stefanov, D. Gajski et al., Electronic System-Level Synthesis Methodologies, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.28, issue.10, pp.1517-1530, 2009.
DOI : 10.1109/TCAD.2009.2026356
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.160.5391

S. Stuijk, Predictable Mapping of Streaming Applications on Multiprocessors, 2007.

L. Cai and D. Gajski, Transaction Level Modeling: an Overview, IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp.19-24, 2003.
DOI : 10.1109/codess.2003.1275250