The impact of technology scaling on lifetime reliability, International Conference on Dependable Systems and Networks, 2004, 2004. ,
DOI : 10.1109/DSN.2004.1311888
A new hybrid fault detection technique for systems-on-a-chip, IEEE Transactions on Computers, vol.55, issue.2, pp.185-198, 2006. ,
DOI : 10.1109/TC.2006.15
Robust system design with built-in soft-error resilience, Computer, vol.38, issue.2, pp.43-52, 2005. ,
DOI : 10.1109/MC.2005.70
Variable threshold CMOS (VTCMOS) in series connected circuits, Proceedings of the 2001 international symposium on Low power electronics and design , ISLPED '01, pp.201-206, 2001. ,
DOI : 10.1145/383082.383133
Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage, IEEE Journal of Solid-State Circuits, vol.37, issue.11, pp.1396-1402, 2002. ,
DOI : 10.1109/JSSC.2002.803949
Reliability enhancement via Sleep Transistors, 2011 12th Latin American Test Workshop (LATW), pp.1-6, 2011. ,
DOI : 10.1109/LATW.2011.5985901
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.379.954
Power-Efficient Application of Sleep Transistors to Enhance the Reliability of Integrated Circuits, Journal of Low Power Electronics, vol.7, issue.4, pp.552-561, 2011. ,
DOI : 10.1166/jolpe.2011.1154
RAMP: A Model for Reliability Aware Microprocessor Design, IBM Research Report, p.23048, 2003. ,
Reliability limits for the gate insulator in CMOS technology, IBM Journal of Research and Development, vol.46, issue.2.3, pp.265-286, 2002. ,
DOI : 10.1147/rd.462.0265
NBTI model for analogue IC reliability simulation, Electronics Letters, vol.46, issue.18, 2010. ,
DOI : 10.1049/el.2010.1971
Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-mode, Microelectronics Reliability, vol.52, issue.9-10, pp.9-10, 2012. ,
DOI : 10.1016/j.microrel.2012.06.149
URL : https://hal.archives-ouvertes.fr/lirmm-00715117
Aging analysis at gate and macro cell level, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp.77-84, 2010. ,
DOI : 10.1109/ICCAD.2010.5654309
A Method of Gate-Level Circuit Reliability Estimation Based on Iterative PTM Model, 2011 IEEE 17th Pacific Rim International Symposium on Dependable Computing, pp.276-277, 2011. ,
DOI : 10.1109/PRDC.2011.45
Unveiling the ISCAS-85 benchmarks: a case study in reverse engineering, IEEE Design & Test of Computers, vol.16, issue.3, pp.72-80, 1999. ,
DOI : 10.1109/54.785838
First results of ITC'99 benchmark circuits, IEEE Design & Test of Computers, vol.17, issue.3, pp.54-59, 2000. ,
DOI : 10.1109/54.867895
New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration, IEEE Transactions on Electron Devices, vol.53, issue.11, pp.2816-2823, 2006. ,
DOI : 10.1109/TED.2006.884077