R. Alur and D. L. Dill, A theory of timed automata, Theoretical Computer Science, vol.126, issue.2, pp.183-235, 1994.
DOI : 10.1016/0304-3975(94)90010-8

G. Behrmann, A. David, and K. G. Larsen, A Tutorial on Uppaal, LNCS, vol.3185, pp.200-236, 2004.
DOI : 10.1007/978-3-540-30080-9_7

D. Beyer, T. Henzinger, R. Jhala, and R. Majumdar, Checking Memory Safety with Blast, Fundamental Approaches to Software Engineering, pp.2-18, 2005.
DOI : 10.1007/978-3-540-31984-9_2

N. Blanc, D. Kroening, and N. Sharygina, Scoot: A Tool for the Analysis of SystemC??Models, LNCS, vol.4963, pp.467-470, 2008.
DOI : 10.1007/978-3-540-78800-3_36

R. Bornat, Proving Pointer Programs in Hoare Logic, MPC. pp. 102 ? 126, 2000.
DOI : 10.1007/10722010_8

A. Cimatti, A. Micheli, I. Narasamdya, and M. Roveri, Verifying SystemC: A software model checking approach, pp.51-59, 2010.

A. Cimatti, A. Griggio, A. Micheli, I. Narasamdya, and M. Roveri, Kratos ??? A Software Model Checker for SystemC, LNCS, vol.65, issue.5, pp.310-316, 2011.
DOI : 10.1007/978-3-540-73370-6_14

E. Cohen, M. Dahlweid, M. Hillebrand, D. Leinenbach, M. Moskal et al., VCC: A Practical System for Verifying Concurrent C, LNCS, vol.41, issue.4, pp.23-42, 2009.
DOI : 10.1007/978-3-540-74591-4_15

H. Garavel, C. Helmstetter, O. Ponsini, and W. Serwe, Verification of an industrial SystemC/TLM model using LOTOS and CADP, 2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design, pp.46-55, 2009.
DOI : 10.1109/MEMCOD.2009.5185377

URL : https://hal.archives-ouvertes.fr/inria-00408283

D. Große, U. Kühne, and R. Drechsler, HW/SW Co-Verification of Embedded Systems using Bounded Model Checking, Great Lakes Symposium on VLSI, pp.43-48, 2006.

A. Habibi, H. Moinudeen, and S. Tahar, Generating Finite State Machines from SystemC, IEEE, pp.76-81, 2006.

P. Herber, A Framework for Automated HW/SW Co-Verification of SystemC Designs using Timed Automata, Logos, 2010.

P. Herber, J. Fellmuth, and S. Glesner, Model checking SystemC designs using timed automata, Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, CODES/ISSS '08, pp.131-136, 2008.
DOI : 10.1145/1450135.1450166

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

P. Herber, M. Pockrandt, and S. Glesner, Transforming SystemC Transaction Level Models into UPPAAL timed automata, Ninth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMPCODE2011), pp.161-170, 2011.
DOI : 10.1109/MEMCOD.2011.5970523

D. Kroening and N. Sharygina, Formal verification of SystemC by automatic hardware/software partitioning, Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2005. MEMOCODE '05., pp.101-110, 2005.
DOI : 10.1109/MEMCOD.2005.1487900

K. L. Man, An Overview of SystemCFL, Research in Microelectronics and Electronics, pp.145-148, 2005.

W. Müller, J. Ruf, and W. Rosenstiel, SystemC: Methodologies and Applications, chap. An ASM based SystemC Simulation Semantics, pp.97-126, 2003.
DOI : 10.1007/b105968

B. Niemann and C. Haubelt, Formalizing TLM with Communicating State Machines. Forum on specification and Design Languages, 2006.

M. Pockrandt, P. Herber, and S. Glesner, Model checking a SystemC/TLM design of the AMBA AHB protocol, 2011 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia, pp.66-75, 2011.
DOI : 10.1109/ESTIMedia.2011.6088527

J. C. Reynolds, Separation logic: a logic for shared mutable data structures, Proceedings 17th Annual IEEE Symposium on Logic in Computer Science, pp.55-74, 2002.
DOI : 10.1109/LICS.2002.1029817

J. Ruf, D. W. Hoffmann, J. Gerlach, T. Kropf, W. Rosenstiel et al., The Simulation Semantics of SystemC, In: DATE. pp. IEEE, pp.64-70, 2001.

A. Salem, Formal semantics of synchronous SystemC, 2003 Design, Automation and Test in Europe Conference and Exhibition, pp.10376-10381, 2003.
DOI : 10.1109/DATE.2003.1253637

C. Traulsen, J. Cornet, M. Moy, and F. Maraninchi:, A SystemC/TLM Semantics in Promela and Its Possible Applications, LNCS, vol.4595, pp.204-222, 2007.
DOI : 10.1007/978-3-540-73370-6_14

URL : https://hal.archives-ouvertes.fr/hal-00294143

H. Tuch, Formal Memory Models for Verifying C Systems Code, 2008.

Y. Zhang, F. Vedrine, and B. Monsuez, SystemC Waiting-State Automata, Proceedings of VECoS 2007, 2007.