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Optimizing Affine Control with Semantic Factorizations

Abstract : Hardware accelerators generated by polyhedral synthesis make an extensive use of affine expressions (affine functions and convex polyhedra) in control and steering logic. Since the control is pipelined, these affine objects must be evaluated at the same time for different values, which forbids aggressive reuse of operators. In this report, we propose an algorithm to factorize a collection of affine expressions without preventing pipelining. Our key contributions are (i) to use semantic factorizations exploiting arithmetic properties of addition and multiplication and (ii) to rely on a cost function whose minimization ensures a correct usage of FPGA resources. Our algorithm is totally parametrized by the cost function, which can be customized to fit a target FPGA. Experimental results on a large pool of linear algebra kernels show a significant improvement compared to traditional low-level RTL optimizations. In particular, we show how our method reduces resource consumption by revealing hidden strength reductions.
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https://hal.inria.fr/hal-01470873
Contributor : Christophe Alias <>
Submitted on : Friday, November 24, 2017 - 5:49:32 PM
Last modification on : Thursday, November 21, 2019 - 2:29:07 AM

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  • HAL Id : hal-01470873, version 3

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Christophe Alias, Alexandru Plesco. Optimizing Affine Control with Semantic Factorizations. ACM Transactions on Architecture and Code Optimization, Association for Computing Machinery, 2017, 14 (4), pp.27. ⟨hal-01470873v3⟩

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