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Optimizing Affine Control with Semantic Factorizations

Abstract : Hardware accelerators generated by polyhedral synthesis make an extensive use of affine expressions (affine functions and convex polyhedra) in control and steering logic. Since the control is pipelined, these affine objects must to be evaluated at the same time for different values, which forbids aggressive reuse of operators. In this report, we propose a method to factorize a collection of affine expressions without preventing pipelining. Our key contributions are (i) to use semantic factorizations exploiting arithmetic properties of addition and multiplication and (ii) to rely on a cost function whose minimization ensures a correct usage of FPGA resources. Our algorithm is totally parametrized by the cost function, which can be customized to fit a target FPGA. Experimental results on a large pool of applications show a significant improvement compared to traditionnal common subexpression factorization. As a bonus, the optimization gain is statistically more regular compared to common subexpression elimination.
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https://hal.inria.fr/hal-01470873
Contributor : Christophe Alias <>
Submitted on : Friday, February 17, 2017 - 7:45:51 PM
Last modification on : Friday, April 20, 2018 - 3:44:27 PM
Long-term archiving on: : Thursday, May 18, 2017 - 3:23:54 PM

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RR-9034.pdf
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  • HAL Id : hal-01470873, version 1

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Christophe Alias, Alexandru Plesco. Optimizing Affine Control with Semantic Factorizations. [Research Report] RR-9034, INRIA Grenoble - Rhone-Alpes. 2017, pp.24. ⟨hal-01470873v1⟩

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