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Speeding Up Galois Field Arithmetic on Intel MIC Architecture
Abstract : Galois Field arithmetic is the basis of LRC, RS and many other erasure coding approaches. Traditional implementations of Galois Field arithmetic use multiplication tables or discrete logarithms, which limit the speed of its computation. The Intel Many Integrated Core (MIC) Architecture provides 60 cores on chip and very wide 512-bit SIMD instructions, attractive for data intensive applications. This paper demonstrates how to leverage SIMD instructions and shared memory multiprocessing on MIC to perform Galois Field arithmetic. The experiments show that the performance of the computation is significantly enhanced.
Cited literature [14 references]
https://hal.inria.fr/hal-01513765
Contributor : Hal Ifip <>
Submitted on : Tuesday, April 25, 2017 - 2:33:31 PM
Last modification on : Tuesday, April 25, 2017 - 2:35:50 PM
Long-term archiving on: : Wednesday, July 26, 2017 - 2:05:09 PM
Contributor : Hal Ifip <>
Submitted on : Tuesday, April 25, 2017 - 2:33:31 PM
Last modification on : Tuesday, April 25, 2017 - 2:35:50 PM
Long-term archiving on: : Wednesday, July 26, 2017 - 2:05:09 PM
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