W. J. Dally and B. Towles, Route packets, not wires: on-chip interconnection networks, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232), pp.684-689, 2001.
DOI : 10.1109/DAC.2001.935594
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.1.5322

L. Benini and G. D. Micheli, Networks on chips: a new SoC paradigm, Computer, vol.35, issue.1, pp.70-78, 2002.
DOI : 10.1109/2.976921
URL : http://infoscience.epfl.ch/record/165542

W. Dally and B. Towles, Principles and Practices of Interconnection Networks, 2003.

M. Lis, K. S. Shim, M. H. Cho, P. Ren, O. Khan et al., DARSIM: a Parallel Cycle-Level NoC Simulator, Proceeding of 6th Annual Workshop on Modeling, Benchmarking and Simulation, 2010.
URL : https://hal.archives-ouvertes.fr/inria-00492982

N. Genko, D. Atienza, G. De-micheli, J. Mendias, R. Hermida et al., A Complete Network-On-Chip Emulation Framework, Design, Automation and Test in Europe, 2005.
DOI : 10.1109/DATE.2005.5
URL : https://hal.archives-ouvertes.fr/hal-00181642

Y. Krasteva, F. Criado, E. De-la-torre, and T. Riesgo, A Fast Emulation-Based NoC Prototyping Framework, 2008 International Conference on Reconfigurable Computing and FPGAs, 2008.
DOI : 10.1109/ReConFig.2008.74
URL : http://oa.upm.es/3345/

G. Schelle and D. Grunwald, Onchip interconnect exploration for multicore processors utilizing FPGAs, Proceedings of 2nd Workshop on Architecture Research using FPGA Platforms, 2006.

P. Wolkotte, P. Holzenspies, and G. Smit, Fast, Accurate and Detailed NoC Simulations, First International Symposium on Networks-on-Chip (NOCS'07), 2007.
DOI : 10.1109/NOCS.2007.18
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.579.3070

M. K. Milo, D. J. Martin, . Sorin, and M. Bradford, Beckmann, etc. Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset, ACM SIGARCH Computer Architecture News, vol.33, pp.92-99, 2005.

D. Wang, N. Enright-jerger, and J. G. Steffan, DART, Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip, NOCS '11, 2011.
DOI : 10.1145/1999946.1999970
URL : https://hal.archives-ouvertes.fr/inria-00494104

E. S. Chung, M. K. Papamichael, E. Nurvitadhi, J. C. Hoe, B. Falsafi et al., ProtoFlex, ACM Transactions on Reconfigurable Technology and Systems, vol.2, issue.2, 2009.
DOI : 10.1145/1534916.1534925

K. Asanovi?, D. Patterson, Z. Tan, A. Waterman, R. Avizienis et al., An FPGA-based Architecture Simulator for Multiprocessors, Proceedings of Design Automation Conference (DAC-2010)

G. X. Liu, G. H. Li, P. Gao, H. Qu, Z. Y. Liu et al., Cycle- Accurate 64+Core FPGA-Based Hybrid Simulator, Proceedings of 5th Annual Workshop on Architectural Research Prototyping, 2010.
URL : https://hal.archives-ouvertes.fr/inria-00494130

N. Jiang, G. Michelogiannakis, and D. Becker, BookSim 2.0 User's Guide Avalaible at https://nocs.stanford.edu/cgi-bin/trac.cgi/raw-attachment, 2003.

S. Berkowits, Pin -A Dynamic Binary Instrumentation Tool Available at http://software.intel.com/en-us/articles/pin-a-dynamic-binary-instrumentation-tool