Fast Legalization for Standard Cell Placement with Simultaneous Wirelength and Displacement Minimization

Abstract : Legalization is one of the most critical steps in modern placement designs. Since several objectives like wirelength, routability, or temperature are already optimized in global placement stage, the objective of legalization is not only to align the cells overlap-free to the rows, but also to preserve the solution of global placement, i.e., the displacement of cells needs to be minimized. However, minimizing displacement only is not enough for current timing-driven SoC designs. Blind displacement minimization may increase the half-perimeter wirelength (HPWL) of nets significantly that degrades the chip performance. In this paper, we propose a fast legalization algorithm for standard cell placement with simultaneous wirelength and displacement minimization. The main contributions of our work are: (1) a fast row selection technique by using k-medoid clustering approach; (2) an exact linear wirelength model to minimize both wirelength and total displacement; (3) a constant time approach to determine the median in trial placement stage. Compared with the state-of-the-art legalization algorithms, experimental results show that our legalizer acquires much better achievement in terms of HPWL, total and maximum displacements, and running time on legalized NTUplace3 global placement results on both ISPD 2005 and 2006 placement contest benchmarks.
Type de document :
Communication dans un congrès
José L. Ayala; David Atienza Alonso; Ricardo Reis. 18th International Conference on Very Large Scale Integration (VLSISOC), Sep 2010, Madrid, Spain. Springer, IFIP Advances in Information and Communication Technology, AICT-373, pp.291-311, 2012, VLSI-SoC: Forward-Looking Trends in IC and Systems Design. 〈10.1007/978-3-642-28566-0_12〉
Liste complète des métadonnées

Littérature citée [21 références]  Voir  Masquer  Télécharger

https://hal.inria.fr/hal-01515992
Contributeur : Hal Ifip <>
Soumis le : vendredi 28 avril 2017 - 14:29:45
Dernière modification le : vendredi 1 décembre 2017 - 01:16:05
Document(s) archivé(s) le : samedi 29 juillet 2017 - 13:38:43

Fichier

978-3-642-28566-0_12_Chapter.p...
Fichiers produits par l'(les) auteur(s)

Licence


Distributed under a Creative Commons Paternité 4.0 International License

Identifiants

Citation

Tsung-Yi Ho, Sheng-Hung Liu. Fast Legalization for Standard Cell Placement with Simultaneous Wirelength and Displacement Minimization. José L. Ayala; David Atienza Alonso; Ricardo Reis. 18th International Conference on Very Large Scale Integration (VLSISOC), Sep 2010, Madrid, Spain. Springer, IFIP Advances in Information and Communication Technology, AICT-373, pp.291-311, 2012, VLSI-SoC: Forward-Looking Trends in IC and Systems Design. 〈10.1007/978-3-642-28566-0_12〉. 〈hal-01515992〉

Partager

Métriques

Consultations de la notice

57

Téléchargements de fichiers

20