Multi-Voltage CMOS Circuit Design, 2006. ,
DOI : 10.1002/0470033371
A Family of 32 nm IA Processors, IEEE Journal of Solid-State Circuits, vol.46, issue.1, pp.119-130, 2011. ,
DOI : 10.1109/JSSC.2010.2079430
1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS, IEEE Journal of Solid-State Circuits, vol.30, issue.8, pp.847-854, 1995. ,
DOI : 10.1109/4.400426
A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs, IEEE Transactions on Circuits and Systems II: Express Briefs, vol.54, issue.7, pp.586-590, 2007. ,
DOI : 10.1109/TCSII.2007.894428
Understanding and minimizing ground bounce during mode transition of power gating structures, Proceedings of the 2003 international symposium on Low power electronics and design , ISLPED '03, pp.22-25, 2003. ,
DOI : 10.1145/871506.871515
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.545.4316
Ground-Bouncing-Noise-Aware Combinational MTCMOS Circuits, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.57, issue.8, pp.2053-2065, 2010. ,
DOI : 10.1109/TCSI.2010.2041505
Threshold Voltage Tuning for Faster Activation With Lower Noise in Tri-Mode MTCMOS Circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems ,
DOI : 10.1109/TVLSI.2011.2110663
Dynamic forward body bias enhanced tri-mode MTCMOS, 2nd Asia Symposium on Quality Electronic Design (ASQED), pp.33-37, 2010. ,
DOI : 10.1109/ASQED.2010.5548161
Sleep transistor forward body bias: An Extra Knob to lower ground bouncing noise in MTCMOS circuits, 2009 International SoC Design Conference (ISOCC), pp.216-219, 2009. ,
DOI : 10.1109/SOCDC.2009.5423813
Reactivation noise suppression with threshold voltage tuning in sequential MTCMOS circuits, 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, pp.347-351, 2010. ,
DOI : 10.1109/VLSISOC.2010.5642685
NOISE-AWARE DATA PRESERVING SEQUENTIAL MTCMOS CIRCUITS WITH DYNAMIC FORWARD BODY BIAS, Journal of Circuits, Systems and Computers, vol.6, issue.01, pp.125-145, 2011. ,
DOI : 10.1109/JSSC.2003.810054
How forward body bias helps to reduce ground bouncing noise and silicon area in MTCMOS circuits: Divulging the basic mechanism, 2010 International SoC Design Conference, pp.9-12, 2010. ,
DOI : 10.1109/SOCDC.2010.5682985
Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.763-773, 2011. ,
DOI : 10.1109/TVLSI.2009.2039761
Reducing Ground-Bounce Noise and Stabilizing the Data-Retention Voltage of Power-Gating Structures, IEEE Transactions on Electron Devices, vol.55, issue.1, pp.197-205, 2008. ,
DOI : 10.1109/TED.2007.911067
Power gating scheduling for power/ground noise reduction, Proceedings of the 45th annual conference on Design automation, DAC '08, pp.980-985, 2008. ,
DOI : 10.1145/1391469.1391716
A Sub-<formula formulatype="inline"><tex Notation="TeX">$\mu$</tex> </formula>s Wake-Up Time Power Gating Technique With Bypass Power Line for Rush Current Support, IEEE Journal of Solid-State Circuits, vol.44, issue.4, pp.1178-1183, 2009. ,
DOI : 10.1109/JSSC.2009.2014201
Zigzag super cut-off CMOS (ZSCCMOS) block activation with self-adaptive voltage level controller: an alternative to clock-gating scheme in leakage dominant era, Proceedings of the IEEE International Solid-State Circuits Conference, pp.400-401, 2003. ,
Charge Recycling in Power-Gated CMOS Circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.27, issue.10, pp.1798-1811, 2008. ,
DOI : 10.1109/TCAD.2008.2003297
URL : http://atrak.usc.edu/~massoud/Papers/CR-MTCMOS-TCAD-08.pdf
Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOS, 8th International Symposium on Quality Electronic Design (ISQED'07), pp.239-244, 2007. ,
DOI : 10.1109/ISQED.2007.47
Low energy MTCMOS with sleep transistor charge recycling, Proceedings of the IEEE International Midwest Symposium on Circuits and Systems, pp.891-894, 2007. ,
A pico-joule class, 1GHz, 32KByte x 64b DSP SRAM with self reverse bias, Proceedings of the IEEE Symposium on VLSl Circuits, pp.253-254, 2003. ,
DOI : 10.1109/vlsic.2003.1221218
SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction, IEEE Journal of Solid-State Circuits, vol.40, issue.4, pp.895-901, 2005. ,
DOI : 10.1109/JSSC.2004.842846
A 32nm 3.1 billion transistor 12-wide-issue Itanium<sup>®</sup> processor for mission-critical servers, 2011 IEEE International Solid-State Circuits Conference, pp.84-85, 2011. ,
DOI : 10.1109/ISSCC.2011.5746230
Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs, IEEE Journal of Solid-State Circuits, vol.42, issue.1, pp.74-83, 2007. ,
DOI : 10.1109/JSSC.2006.885057
A 40 nm 16-Core 128-Thread SPARC SoC Processor, IEEE Journal of Solid-State Circuits, vol.46, issue.1, pp.131-144, 2011. ,
DOI : 10.1109/JSSC.2010.2080491
POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor, IEEE Journal of Solid-State Circuits, vol.46, issue.1, pp.145-161, 2011. ,
DOI : 10.1109/JSSC.2010.2080611
A leakage reduction methodology for distributed MTCMOS, IEEE Journal of Solid-State Circuits, vol.39, issue.5, pp.818-826, 2004. ,
DOI : 10.1109/JSSC.2004.826335
Transistor sizing issues and tool for multithreshold CMOS technology, Proceedings of the IEEE /ACM International Design Automation Conference, pp.409-414, 1997. ,
DOI : 10.1109/dac.1997.597182
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.117.1608
A 1-V high-speed MTCMOS circuit scheme for power-down application circuits, IEEE Journal of Solid-State Circuits, vol.32, issue.6, pp.861-869, 1997. ,
DOI : 10.1109/4.585288
MTCMOS with outer feedback (MTOF) flip-flops, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03., pp.429-432, 2003. ,
DOI : 10.1109/ISCAS.2003.1206305
New MTCMOS Flip-Flops with Simple Control Circuitry and Low Leakage Data Retention Capability, 2007 14th IEEE International Conference on Electronics, Circuits and Systems, pp.1276-1279, 2007. ,
DOI : 10.1109/ICECS.2007.4511230
Low-Leakage and Compact Registers with Easy-Sleep Mode, Journal of Low Power Electronics, vol.6, issue.2, pp.263-279, 2010. ,
DOI : 10.1166/jolpe.2010.1080
Power gated SRAM circuits with data retention capability and high immunity to noise: A comparison for reliability in low leakage sleep mode, 2010 International SoC Design Conference, pp.5-8, 2010. ,
DOI : 10.1109/SOCDC.2010.5682988
Asymmetrical ground gating for low leakage and data robust sleep mode in memory banks, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, pp.205-208, 2011. ,
DOI : 10.1109/VDAT.2011.5783611
Design and Optimization of Power-Gated Circuits With Autonomous Data Retention, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.227-236, 2011. ,
DOI : 10.1109/TVLSI.2009.2033356
Microarchitectural techniques for power gating of execution units, Proceedings of the 2004 international symposium on Low power electronics and design , ISLPED '04, pp.32-37, 2004. ,
DOI : 10.1145/1013235.1013249
Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.1215-1224, 2007. ,
DOI : 10.1109/TVLSI.2007.904101
Managing static leakage energy in microprocessor functional units, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings., pp.321-332, 2002. ,
DOI : 10.1109/MICRO.2002.1176260
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.11.5021
Domino logic with dynamic body biased keeper, Proceedings of the European Solid-State Circuits Conference, pp.675-678, 2002. ,
DOI : 10.1109/tvlsi.2003.817515
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.138.6153
Forward body biased keeper for enhanced noise immunity in domino logic circuits, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), pp.917-920, 2004. ,
DOI : 10.1109/ISCAS.2004.1329422
Ultra-low voltage circuits and processor in 180nm to 90nm technologies with a swappedbody biasing technique, Proceedings of the IEEE International Solid-State Circuits Conference, pp.156-518, 2004. ,
Forward body bias for microprocessors in 130-nm technology generation and beyond, IEEE Journal of Solid-State Circuits, vol.38, issue.5, pp.696-701, 2003. ,
DOI : 10.1109/JSSC.2003.810054
Characterization of a novel nine transistor SRAM cell, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.488-492, 2008. ,
High Read Stability and Low Leakage Cache Memory Cell, 2007 IEEE International Symposium on Circuits and Systems, pp.2774-2777, 2007. ,
DOI : 10.1109/ISCAS.2007.378628
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.468.1640
Low power and robust 7T dual-V<inf>t</inf> SRAM circuit, 2008 IEEE International Symposium on Circuits and Systems, pp.1452-1455, 2008. ,
DOI : 10.1109/ISCAS.2008.4541702
Application-specific selection of 6T SRAM cells offering superior performance and quality with a triple-threshold-voltage CMOS technology, 2011 3rd Asia Symposium on Quality Electronic Design (ASQED), 2011. ,
DOI : 10.1109/ASQED.2011.6111704
Leakage-Aware Design of Nanometer SoC, 2007 IEEE International Symposium on Circuits and Systems, pp.3231-3234, 2007. ,
DOI : 10.1109/ISCAS.2007.378160
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.461.5919
Ground bounce in digital VLSI circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.180-185, 2003. ,
DOI : 10.1109/TVLSI.2003.810785
URL : http://atrak.usc.edu/~massoud/Papers/groundbounce-journal.pdf