J. Albericio, R. Gran, P. Ibáñezib´ibáibá?ibáñez, V. Viñalsvi?viñals, and J. M. Llabería, ABS, ACM Transactions on Architecture and Code Optimization, vol.8, issue.4, 2012.
DOI : 10.1145/2086696.2086698

C. Bienia, Benchmarking Modern Multiprocessors, 2011.

R. Bitirgen, E. Ipek, and J. F. Martinez, Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach, 2008 41st IEEE/ACM International Symposium on Microarchitecture, pp.318-3294771801, 2008.
DOI : 10.1109/MICRO.2008.4771801

S. Kristof-du-bois, J. B. Eyerman, L. Sartor, and . Eeckhout, Criticality Stacks: Identifying Critical Threads in Parallel Programs Using Synchronization Behavior, Proceedings of the 40th Annual International Symposium on Computer Architecture (ISCA '13, pp.511-522, 2013.

E. Ebrahimi, C. Lee, O. Mutlu, and Y. N. Patt, Prefetch-aware Shared Resource Management for Multi-core Systems, Proceedings of the 38th Annual International Symposium on Computer Architecture (ISCA '11, pp.141-152, 2011.

E. Ebrahimi, O. Mutlu, C. J. Lee, and Y. N. Patt, Coordinated control of multiple prefetchers in multi-core systems, Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, Micro-42, pp.316-326, 2009.
DOI : 10.1145/1669112.1669154

J. L. Henning, SPEC CPU2006 benchmark descriptions, ACM SIGARCH Computer Architecture News, vol.34, issue.4, pp.1-17, 2006.
DOI : 10.1145/1186736.1186737

I. Hur and C. Lin, Memory Prefetching Using Adaptive Stream Detection, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06), pp.397-408, 2006.
DOI : 10.1109/MICRO.2006.32

I. Hur and C. Lin, Feedback mechanisms for improving probabilistic memory prefetching, 2009 IEEE 15th International Symposium on High Performance Computer Architecture, pp.443-454, 2009.
DOI : 10.1109/HPCA.2009.4798282

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.140.2283

Y. Ishii, M. Inaba, and K. Hiraki, Access map pattern matching for data cache prefetch, Proceedings of the 23rd international conference on Conference on Supercomputing, ICS '09, pp.499-500, 2009.
DOI : 10.1145/1542275.1542349

Y. Ishii, M. Inaba, and K. Hiraki, Unified memory optimizing architecture, Proceedings of the 26th ACM international conference on Supercomputing, ICS '12, pp.267-278, 2012.
DOI : 10.1145/2304576.2304614

A. Jaleel, K. B. Theobald, S. C. Steely, J. , and J. Emer, High Performance Cache Replacement Using Re-reference Interval Prediction (RRIP), Proceedings of the 37th Annual International Symposium on Computer Architecture (ISCA '10, pp.60-71, 2010.
DOI : 10.1145/1816038.1815971

A. Jimenez, P. Buyuktosunoglu, F. P. Bose, F. O-'connell, M. Cazorla et al., Increasing multicore system efficiency through intelligent bandwidth shifting, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA), pp.39-50, 2015.
DOI : 10.1109/HPCA.2015.7056020

URL : http://hdl.handle.net/2117/84776

V. Jiménez, R. Gioiosa, F. J. Cazorla, A. Buyuktosunoglu, P. Bose et al., Making data prefetch smarter, Proceedings of the 21st international conference on Parallel architectures and compilation techniques, PACT '12, 2012.
DOI : 10.1145/2370816.2370837

D. Joseph and D. Grunwald, Prefetching using Markov predictors, ACM SIGARCH Computer Architecture News, vol.25, issue.2, pp.252-263, 1997.
DOI : 10.1145/384286.264207

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.637.7652

P. Norman and . Jouppi, Improving Direct-mapped Cache Performance by the Addition of a Small Fully-associative Cache and Prefetch Buffers, Proceedings of the 17th Annual International Symposium on Computer Architecture (ISCA '90, pp.364-373, 1990.

D. Kroft, Lockup-free instruction fetch/prefetch cache organization, 25 years of the international symposia on Computer architecture (selected papers) , ISCA '98, pp.81-87, 1981.
DOI : 10.1145/285930.285979

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.301.1286

A. Lai, C. Fide, and B. Falsafi, Dead-block Prediction &Amp; Dead-block Correlating Prefetchers, Proceedings of the 28th Annual International Symposium on Computer Architecture (ISCA '01, pp.144-154, 2001.
DOI : 10.1145/384285.379259

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.23.7412

C. Lee, O. Mutlu, V. Narasiman, and Y. N. Patt, Prefetch-Aware DRAM Controllers, 2008 41st IEEE/ACM International Symposium on Microarchitecture, pp.200-209, 2008.
DOI : 10.1109/MICRO.2008.4771791

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.143.6248

F. Liu and Y. Solihin, Studying the impact of hardware prefetching and bandwidth partitioning in chip-multiprocessors, Proceedings of the ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems, SIGMETRICS '11, pp.37-48, 2011.
DOI : 10.1145/1993744.1993749

J. Kun-luo, M. Gummaraju, and . Franklin, Balancing thoughput and fairness in SMT processors In Performance Analysis of Systems and Software, ISPASS. 2001 IEEE International Symposium on, pp.164-171990695, 2001.

P. Michaud, Best-offset hardware prefetching, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), pp.469-480, 2016.
DOI : 10.1109/HPCA.2016.7446087

URL : https://hal.archives-ouvertes.fr/hal-01254863

R. Natarajan and M. Chaudhuri, Characterizing multi-threaded applications for designing sharingaware last-level cache replacement policies, 2013 IEEE International Symposium on Workload Characterization (IISWC). 1?10, 2013.
DOI : 10.1109/iiswc.2013.6704665

K. J. Nesbit, J. Laudon, and J. E. Smith, Virtual Private Caches, Proceedings of the 34th Annual International Symposium on Computer Architecture (ISCA '07, pp.57-68, 2007.
DOI : 10.1145/1273440.1250671

J. Kyle, J. E. Nesbit, and . Smith, Data Cache Prefetching Using a Global History Buffer, Proceedings of the 10th International Symposium on High Performance Computer Architecture, 2004.

A. V. Oppenheim, A. S. Willsky, and S. H. Nawab, Signals &Amp; Systems, 1996.

S. Palacharla and R. E. Kessler, Evaluating stream buffers as a secondary cache replacement, ACM SIGARCH Computer Architecture News, vol.22, issue.2, pp.24-33, 1994.
DOI : 10.1145/192007.192014

URL : http://byte.csc.lsu.edu/~durresi/7080/reading/p24-palacharla.pdf

B. Panda, SPAC:A Synergistic Prefetcher Aggressiveness Controller for Multi-core Systems, IEEE Transactions on Computers, pp.99-100, 2016.
DOI : 10.1109/TC.2016.2547392

URL : https://hal.archives-ouvertes.fr/hal-01307538

B. Panda and S. Balachandran, CSHARP: Coherence and SHaring Aware Cache Replacement Policies for Parallel Applications, 2012 IEEE 24th International Symposium on Computer Architecture and High Performance Computing, pp.252-259, 2012.
DOI : 10.1109/SBAC-PAD.2012.27

B. Panda and S. Balachandran, TCPT - Thread criticality-driven prefetcher throttling, Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, pp.399-399, 2013.
DOI : 10.1109/PACT.2013.6618835

B. Panda and S. Balachandran, CAFFEINE, ACM Transactions on Architecture and Code Optimization, vol.12, issue.3, 2015.
DOI : 10.1145/2806891

H. Pugsley, Z. Chishti, C. Wilkerson, P. F. Chuang, R. L. Scott et al., Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers, 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA), pp.626-637, 2014.
DOI : 10.1109/HPCA.2014.6835971

S. Rixner, W. J. Dally, U. J. Kapasi, P. Mattson, and J. D. Owens, Memory access scheduling, ACM SIGARCH Computer Architecture News, vol.28, issue.2, pp.128-138, 2000.
DOI : 10.1145/342001.339668

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.25.9673

V. Seshadri, . Yedkar, . Xin, P. B. Mutlu, M. A. Gibbons et al., Mitigating Prefetcher-Caused Pollution Using Informed Caching Policies for Prefetched Blocks, ACM Transactions on Architecture and Code Optimization, vol.11, issue.4, 2015.
DOI : 10.1145/2677956

K. Sharma, M. Shevgoor, S. Koladiya, R. Balasubramonian, C. Wilkerson et al., Text Book Of Correlations And Regression Discovery Publishing House. https://books. google.fr/books?id=obb7\ 6k6XDQC Efficiently Prefetching Complex Address Patterns, Proceedings of the 48th International Symposium on Microarchitecture (MICRO-48, pp.141-152, 2005.

R. Sinharoy, W. J. Kalla, H. Q. Starke, R. Le, J. A. Cargnoni et al., IBM POWER7 multicore server processor, IBM Journal of Research and Development, vol.55, issue.3, pp.1-1, 2011.
DOI : 10.1147/JRD.2011.2127330

J. Smith, Sequential Program Prefetching in Memory Hierarchies, Computer, vol.11, issue.12, pp.7-21, 1978.
DOI : 10.1109/C-M.1978.218016

O. Srinath, H. Mutlu, Y. N. Kim, and . Patt, Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers, 2007 IEEE 13th International Symposium on High Performance Computer Architecture, pp.63-74, 2007.
DOI : 10.1109/HPCA.2007.346185

R. A. Velasquez, P. Michaud, and A. Seznec, BADCO: Behavioral Application-Dependent Superscalar Core Model, SAMOS XII: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation. Samos, Greece, 2012.
DOI : 10.1109/samos.2012.6404158

URL : https://hal.archives-ouvertes.fr/hal-00707346

A. Wu, M. Jaleel, S. C. Martonosi, J. Steely, and J. Emer, PACMan, Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-44 '11, pp.442-453, 2011.
DOI : 10.1145/2155620.2155672

X. Zhuang and H. H. Lee, A hardware-based cache pollution filtering mechanism for aggressive prefetches, 2003 International Conference on Parallel Processing, 2003. Proceedings., pp.286-293, 2003.
DOI : 10.1109/ICPP.2003.1240591

URL : http://arch.ece.gatech.edu/pub/icpp03.pdf