A Low-Power Ultra-Fast Capacitor-Less LDO with Advanced Dynamic Push-Pull Techniques

Abstract : A current-efficient, capacitor-less low-dropout regulator (LDO) with fast-transient response for portable applications is presented in this chapter. It makes use of an adaptive biasing common-gate amplifier to extend loop bandwidth of the LDO at heavy loads greatly. Also, the dynamic push-pull (DPP) slew-rate enhancement (SRE) circuit based on capacitive coupling detects rapid voltage spikes at the output to provide an extra current to charge and discharge the large gate capacitance of the power transistor momentarily. The proposed circuit has been implemented in a 0.35μm standard CMOS process. Experimental results show that it can deliver 100mA load current at 150mV dropout voltage. It only consumes 10μA quiescent current at no-load condition and is able to recover within 0.8μs even under the maximum load current change.
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Salvador Mir; Chi-Ying Tsui; Ricardo Reis; Oliver C. S. Choy. 19th International Conference on Very Large Scale Integration (VLSISOC), Oct 2011, Hong Kong, China. Springer, IFIP Advances in Information and Communication Technology, AICT-379, pp.34-51, 2012, VLSI-SoC: Advanced Research for Systems on Chip. 〈10.1007/978-3-642-32770-4_3〉
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Xin Ming, Ze-Kun Zhou, Bo Zhang. A Low-Power Ultra-Fast Capacitor-Less LDO with Advanced Dynamic Push-Pull Techniques. Salvador Mir; Chi-Ying Tsui; Ricardo Reis; Oliver C. S. Choy. 19th International Conference on Very Large Scale Integration (VLSISOC), Oct 2011, Hong Kong, China. Springer, IFIP Advances in Information and Communication Technology, AICT-379, pp.34-51, 2012, VLSI-SoC: Advanced Research for Systems on Chip. 〈10.1007/978-3-642-32770-4_3〉. 〈hal-01519764〉

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