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Conference Papers Year : 2012

Modeling of Syllogisms in Analog Hardware

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Darko Kovacevic
  • Function : Author
  • PersonId : 1008051
Nikica Pribacic
  • Function : Author
  • PersonId : 1008052
Mate Jovic
  • Function : Author
  • PersonId : 1008053

Abstract

Syllogistic reasoning is modeled in analog hardware and some hardware models, i.e. syllogisms Baroco and Darii are presented. Chaining of syllogisms is modeled by using original min-max entities (circuits), “to see” whether the two rules, modeled in dedicated hardware, i.e., IF A THEN B and IF B THEN C imply the “hardware” rule IF A THEN C. The preliminaries include original min-max circuits based on operational amplifiers (Op-Amp), straight lines Op-Amp generators and different test circuits designed in Electronics WorkBench simulation environment and in real hardware. The “stage” to perform modeling is the phase plane.
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Dates and versions

hal-01521430 , version 1 (11-05-2017)

Licence

Attribution - CC BY 4.0

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Darko Kovacevic, Nikica Pribacic, Radovan Antonic, Asja Kovacevic, Mate Jovic. Modeling of Syllogisms in Analog Hardware. 8th International Conference on Artificial Intelligence Applications and Innovations (AIAI), Sep 2012, Halkidiki, Greece. pp.443-452, ⟨10.1007/978-3-642-33409-2_46⟩. ⟨hal-01521430⟩
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