L. Codrescu and D. Wills, S: Architecture of the Atlas chip-multiprocessor: dynamically parallelizing irregular applications, ICCD '99) International Conference on, pp.10-1109808577, 1999.

K. Rakesh, V. Victor, . Zyuban, and M. Dean, Tullse: Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling, International Symposium on Computer Architecture -ISCA DOI: 10.1109/ISCA, pp.408-41934, 2005.

A. Ahmed, A. K. Jones, and M. Rami, Codesign of NoC and Cache Organization for Reducing Access Latency in Chip Multiprocessors, IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, vol.23, p.2012

J. William and B. T. Dally, Route Packets, Not Wires: On-Chip Interconnection Networks, Proceedings of the 38th Design Automation Conference, pp.681-689, 2001.

D. Ching, P. Schaumont, and I. Verbauwhede, Integrated Modeling and Generation of a Configurable network-on-chip, Proceedings. 18th International Parallel and Distributed Processing Symposium, 2004.

A. Hemani, A network on chip architecture and design methodology, Proc. Symposium on VLSI, pp.117-124, 2002.

S. Feng, J. Weixing, Q. Baojun, L. Bin, and . R. Haroon, A Triplet Based Computer Architecture Supporting Parallel Object Computing, Proceedings of the Eighteenth International Conference on ASAP, pp.192-197, 2007.

Q. Baojun, S. Feng, and J. Weixing, A New Routing Algorithm in Triple-Based Hierarchical Interconnection Network, First International Conference on Innovative Computing, Information and Control, Volume I (ICICIC'06), pp.725-728, 2006.
DOI : 10.1109/ICICIC.2006.17

L. Bin, T. Zhi-chen, and G. Yu-jin, Triplet-based architecture and its process migration mechanism, 2009 International Conference on Machine Learning and Cybernetics, 2009.
DOI : 10.1109/ICMLC.2009.5212644

Y. Dong, D. Wang, and W. Zheng, Exact Computation Of The Mean Minimal Path Length Of N-MESH AND N-TORUS, Journal of Software, vol.20, issue.4, 1997.

J. Weixing, S. Feng, Q. Baojun, and B. Liu, Study on an interconnection network for complex embedded systems, Chinese High Technology Letters, vol.17, issue.9, pp.886-890, 2007.

S. Dandamudi and D. Eager, Hierarchical interconnection networks for multicomputer systems, IEEE Transactions on Computers, vol.39, issue.6, pp.786-797, 1990.
DOI : 10.1109/12.53600

M. Kyu, J. *. , D. Hyun, Y. Dam, S. Mike et al., Balancing DRAM Locality and Parallelism in Shared Memory CMP Systems, High Performance Computer Architecture (HPCA), 2012 IEEE 18th International Symposium

M. Kandemir, Data locality enhancement for CMPs, 2007 IEEE/ACM International Conference on Computer-Aided Design, 2007.
DOI : 10.1109/ICCAD.2007.4397259

G. Bikshandi, G. Jia, and H. Daniel, Programming for parallelism and locality with hierarchically tiled arrays, Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming , PPoPP '06, 2006.
DOI : 10.1145/1122971.1122981

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.119.2791

V. Xavier, B. Nerina, L. Josep, and G. Antonio, A fast and accurate framework to analyze and optimize cache memory behavior, TOPLAS, 2004.

B. Abhinav and V. Laxmikant, Benefits of Topology Aware Mapping For Mesh Interconnects . Parallel Processing Letters, 2010.

B. Abhinav, B. Eric, and V. Laxmikant, Kale :Optimizing communication for Charm++ applications by reducing network contention, 1{7 Prepared using cpeauth.cls [Version, 0192.

C. Zhang, Z. Yutao, and W. Youfeng, A hierarchical model of data locality, Proc. POPL, 2006.