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A Many-core Parallelizing Processor

Katarzyna Porada 1 Bernard Goossens 1 
1 DALI - Digits, Architectures et Logiciels Informatiques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, UPVD - Université de Perpignan Via Domitia
Abstract : This paper presents a new many-core processor design to parallelize by hardware. The parallel run is built from a deterministic parallelization of the sequential trace, hence inheriting its order. The code pieces are distributed according to the sequential order in a way which favors neighbor cores communications. The ordered placement simplifies the processor interconnect and the memory sharing. The paper presents a VHDL implementation of a 64-core version of the processor. The synthesized prototype proves that the automatic parallelization technique works and the speed and size of the synthesis show that the design is scalable.
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Reports (Technical report)
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Submitted on : Friday, July 7, 2017 - 3:19:00 PM
Last modification on : Wednesday, October 26, 2022 - 8:13:51 AM
Long-term archiving on: : Wednesday, January 24, 2018 - 7:03:11 AM


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  • HAL Id : hal-01558374, version 1



Katarzyna Porada, Bernard Goossens. A Many-core Parallelizing Processor . [Technical Report] Université de Perpignan Via Domita. 2017. ⟨hal-01558374⟩



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