Techniques for Architecture Design for Binary Arithmetic Decoder Engines Based on Bitstream Flow Analysis

Abstract : The design and implementation of a hardware accelerator dedicated to Binary Arithmetic Decoding Engine (BADE) is presented. This is the main module of the Context-Adaptive Binary Arithmetic Decoder (CABAD), as used in the H.264/AVC on-chip video decoders. We propose and implement a new approach for accelerating the decoding hardware of the significance map by providing the correct context for the regular hardware engine of the (CABAD). The design development was based on a large set of software experiments, which aimed at exploiting the characteristic behavior of the bitstream during decoding. The analysis gave new insights to propose a new hardware architecture to improve throughput of regular engines for significance map with low silicon area overhead. The proposed solution was described in VHDL and synthesized to standard cells in IBM 0.18 μm CMOS process. The results show that the developed architecture reaches 187 MHz with a non optimized physical synthesis.
Type de document :
Communication dans un congrès
Jürgen Becker; Marcelo Johann; Ricardo Reis. 17th International Conference on Very Large Scale Integration (VLSISOC), Oct 2009, Florianópolis, Brazil. Springer, IFIP Advances in Information and Communication Technology, AICT-360, pp.181-197, 2011, VLSI-SoC: Technologies for Systems Integration. 〈10.1007/978-3-642-23120-9_10〉
Liste complète des métadonnées

Littérature citée [12 références]  Voir  Masquer  Télécharger

https://hal.inria.fr/hal-01569361
Contributeur : Hal Ifip <>
Soumis le : mercredi 26 juillet 2017 - 15:40:15
Dernière modification le : vendredi 1 décembre 2017 - 01:15:57

Fichier

978-3-642-23120-9_10_Chapter.p...
Fichiers produits par l'(les) auteur(s)

Licence


Distributed under a Creative Commons Paternité 4.0 International License

Identifiants

Citation

Dieison Deprá, Sergio Bampi. Techniques for Architecture Design for Binary Arithmetic Decoder Engines Based on Bitstream Flow Analysis. Jürgen Becker; Marcelo Johann; Ricardo Reis. 17th International Conference on Very Large Scale Integration (VLSISOC), Oct 2009, Florianópolis, Brazil. Springer, IFIP Advances in Information and Communication Technology, AICT-360, pp.181-197, 2011, VLSI-SoC: Technologies for Systems Integration. 〈10.1007/978-3-642-23120-9_10〉. 〈hal-01569361〉

Partager

Métriques

Consultations de la notice

63

Téléchargements de fichiers

21