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A SAR Pipeline ADC Embedding Time Interleaved DAC Sharing for Ultra-low Power Camera Front Ends

Abstract : The growing need for ultra-low power cameras for sensors, surveillance and consumer applications has resulted in significant advances in compressed domain data acquisition from pixel arrays. In this journal we present a novel 64-input Successive Approximation (SAR) Pipeline analog-to-digital converter (ADC) suitable for compressed domain data acquisition in camera front-ends. The proposed architecture features a time interleaved capacitive digital-to-analog converter (DAC) shared between column parallel ADCs for area savings (2.28X); and a shared amplifier stage for power savings (60 %), achieving 4X throughput as compared to traditional architectures. Simulations on a 130 nm foundry process shows that the proposed SAR Pipeline ADC draws 31 $$\upmu $$W at 2 MS/s having a target Figure-of-Merit (FOM) of 87 fJ/conv. per step at Nyquist rate. The proposed compressive sensing front end achieves per patch energy per patch of 0.9 nJ.
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Anvesha Amaravati, Manan Chugh, Arijit Raychowdhury. A SAR Pipeline ADC Embedding Time Interleaved DAC Sharing for Ultra-low Power Camera Front Ends. 23th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2015, Daejeon, South Korea. pp.131-149, ⟨10.1007/978-3-319-46097-0_7⟩. ⟨hal-01578616⟩



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