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Parallel Custom Instruction Identification for Extensible Processors

Abstract : With the ability of customization for an application domain, extensible processors have been used more and more in embedded systems in recent years. Extensible processors customize an application domain by executing parts of application code in hardware instead of software. Determining parts of application code as custom instruction generally requires subgraph enumeration and subgraph selection. Both subgraph enumeration problem and subgraph selection problem are computationally difficult problems. Most of previous works focus on sequential algorithms for these two problems. In this paper, we present a parallel implementation of a latest subgraph enumeration algorithm based on a computer cluster. A standard ant colony optimization algorithm (ACO), a modified version of ACO with local optimum search and a parallel ACO algorithm are also proposed to solve the subgraph selection problem in this work. Experimental results show that the parallel algorithms outperform the sequential algorithms in terms of runtime or (and) quality of results. In addition, we have formally proved the upper bound on the number of feasible solutions in subgraph selection problem with or without the overlapping constraint.
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https://hal.inria.fr/hal-01587020
Contributor : Emmanuel Casseau <>
Submitted on : Wednesday, September 13, 2017 - 3:18:53 PM
Last modification on : Wednesday, June 24, 2020 - 4:19:44 PM

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Chenglong Xiao, Shanshan Wang, Wanjun Liu, Emmanuel Casseau. Parallel Custom Instruction Identification for Extensible Processors. Journal of Systems Architecture, Elsevier, 2017, 76, pp.149-159. ⟨10.1016/j.sysarc.2016.11.011⟩. ⟨hal-01587020⟩

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