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Energy-Aware Hardware Implementation of Network Coding

Abstract : In the last few years, Network Coding (NC) has been shown to provide several advantages, both in theory and in practice. However, its applicability to battery-operated systems under strict power constraints has not been proven yet, since most implementations are based on high-end CPUs and GPUs. This work represents the first effort to bridge NC theory with real-world, low-power applications. In this paper, we provide a detailed analysis on the energy consumption of NC, based on VLSI design measurements, and an approach for specifying optimal algorithmic parameters, such as field size, minimizing the required energy for both transmission and coding of data. Our custom, energy-aware NC accelerator proves the feasibility of incorporating NC into modern, low-power systems; the proposed architecture achieves a coding throughput of 80MB/s (60MB/s), while consuming 22uW (12.5mW) for the encoding (decoding) process.
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https://hal.inria.fr/hal-01587833
Contributor : Hal Ifip <>
Submitted on : Thursday, September 14, 2017 - 4:48:04 PM
Last modification on : Thursday, September 14, 2017 - 4:53:14 PM
Long-term archiving on: : Friday, December 15, 2017 - 8:25:45 PM

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Georgios Angelopoulos, Muriel Médard, Anantha Chandrakasan. Energy-Aware Hardware Implementation of Network Coding. International IFIP TC 6 Workshops PE-CRN, NC-Pro, WCNS, and SUNSET 2011 Held at NETWORKING 2011 (NETWORKING), May 2011, Valencia, Spain. pp.137-144, ⟨10.1007/978-3-642-23041-7_14⟩. ⟨hal-01587833⟩

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