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Conference Papers Year : 2011

Reorder the Write Sequence by Virtual Write Buffer to Extend SSD’s Lifespan

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Fang Liu
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  • PersonId : 1017404
Yimo Du
  • Function : Author
  • PersonId : 1017405


The limited lifespan is the Achilles’s heel of Solid State Drive (SSD) based on NAND flash memory. NAND flash has two drawbacks that degrade SSD’s lifespan. One is the out-of-place update. Another is the sequential write constraint within a block. To extend the lifespan, SSD usually employs a write buffer to reduce write traffic to flash memory. However, existing write buffer schemes only pay attention to the first drawback, but fail to overcome the second one. We propose a virtual write buffer architecture, which covers the two aspects simultaneously. The virtual buffer consists of two components, DRAM and the reorder area. DRAM is the normal write buffer which aims at the first drawback. It endeavors to reduce write traffic to flash memory as much as possible by pursuing higher hit ratio. The reorder area is actually a part of SSD’s flash address space. It focuses on reordering write sequence directed to flash chip. Reordering write sequence helps to overcome the second drawback. The two components work together just like the virtual memory adopted by operating system. So, we name the architecture as virtual write buffer. Our virtual write buffer outperforms traditional write buffers because of two reasons. First, the DRAM can adopt any existing superior cache replacement policy, it achieves higher hit ratio than traditional write buffers do. Second, the virtual write buffer reorders the write sequence, which hasn’t been exploited by traditional write buffers. We compare the virtual write buffer with others by trace-driven simulations. Experimental results show that, SSDs employing the virtual buffer survive longer lifespan on most workloads.
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hal-01593016 , version 1 (25-09-2017)


Attribution - CC BY 4.0



Zhiguang Chen, Fang Liu, Yimo Du. Reorder the Write Sequence by Virtual Write Buffer to Extend SSD’s Lifespan. 8th Network and Parallel Computing (NPC), Oct 2011, Changsha,, China. pp.263-276, ⟨10.1007/978-3-642-24403-2_21⟩. ⟨hal-01593016⟩
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