V. F. Pavlidis and E. G. , 3-D Topologies for Networks-on-Chip, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.15, issue.10, pp.1081-1090, 2007.
DOI : 10.1109/TVLSI.2007.893649

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

W. R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua et al., Demystifying 3D ICs: The Pros and Cons of Going Vertical, IEEE Design and Test of Computers, vol.22, issue.6, pp.498-511, 2005.
DOI : 10.1109/MDT.2005.136

J. Kim, C. Nicopoulos, D. Park, R. Das, Y. Xie et al., A novel dimensionally-decomposed router for on-chip communication in 3D architectures, ACM SIGARCH Computer Architecture News, vol.35, issue.2, pp.138-149, 2007.
DOI : 10.1145/1273440.1250680

C. Addo-quaye, Thermal-aware mapping and placement for 3-D NoC designs, 2005 Joint 30th International Conference on Infrared and Millimeter Waves and 13th International Conference on Terahertz Electronics, pp.25-28, 2005.
DOI : 10.1109/SOCC.2005.1554447

C. L. Chou and R. Marculescu, Run-Time Task Allocation Considering User Behavior in Embedded Multiprocessor Networks-on-Chip, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.29, issue.1, pp.78-91, 2010.
DOI : 10.1109/TCAD.2009.2034348

C. L. Chou, U. Y. Ogras, and R. Marculescu, Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.27, issue.10, pp.1866-1879, 2008.
DOI : 10.1109/TCAD.2008.2003301

H. Matsutani, M. Koibuchi, and H. Amano, Tightly-Coupled Multi-Layer Topologies for 3-D NoCs, 2007 International Conference on Parallel Processing (ICPP 2007), pp.75-85, 2007.
DOI : 10.1109/ICPP.2007.79

B. S. Feero and P. P. , Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation, IEEE Transactions on Computers, vol.58, issue.1, pp.32-45, 2009.
DOI : 10.1109/TC.2008.142

D. Park, S. Eachempati, R. Das, A. K. Mishra, Y. Xie et al., MIRA, Int'l Symp. Computer Architecture, pp.251-261, 2008.
DOI : 10.1145/1394608.1382143

X. Wang, M. Yang, Y. Jiang, and P. Liu, A power-aware mapping approach to map IP cores onto NoCs under bandwidth and latency constraints, ACM Transactions on Architecture and Code Optimization, vol.7, issue.1, pp.1-31, 2009.
DOI : 10.1145/1736065.1736066

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

A. H. Land and A. G. Doig, An Automatic Method of Solving Discrete Programming Problems, Econometrica, vol.28, issue.3, pp.497-520, 1960.
DOI : 10.2307/1910129

J. Hu and R. Marculescu, Energy-and performance-aware mapping for regular NoC architectures, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol.24, issue.4, pp.551-562, 2005.

L. T. Smit, G. J. Smit, J. L. Hurink, H. Broersma, D. Paulusma et al., Wolkotte: Run-time assignment of tasks to multiple heterogeneous processors, Progress Embedded System Symp, pp.185-192, 2004.

E. Carvalho, N. Calazans, and F. Moraes, Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs, 18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07), pp.34-40, 2007.
DOI : 10.1109/RSP.2007.26

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

V. Lo, K. J. Windisch, W. Liu, and B. , Noncontiguous processor allocation algorithms for mesh-connected multicomputers, IEEE Transactions on Parallel and Distributed Systems, vol.8, issue.7, pp.712-726, 1997.
DOI : 10.1109/71.598346

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

R. Dick, Embedded system synthesis benchmarks suite(E3S) [Online] Available: http://ziyang.eecs.umich, 2002.

. Noxim, Available: http://noxim.sourceforge.net