J. A. Ambrose, S. Parameswaran, and A. Ignjatovic, MUTE-AES: A multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm, 2008 IEEE/ACM International Conference on Computer-Aided Design, pp.678-684, 2008.
DOI : 10.1109/ICCAD.2008.4681650

L. Barthe, P. Benoit, and L. Torres, Investigation of a Masking Countermeasure against Side-Channel Attacks for RISC-based Processor Architectures, 2010 International Conference on Field Programmable Logic and Applications, pp.139-144, 2010.
DOI : 10.1109/FPL.2010.35
URL : https://hal.archives-ouvertes.fr/lirmm-00548802

G. Research, . Grlib, . Ip-library-user-'s, and . Manual, Available online at http: //www.gaisler.com/products/grlib/grlib.pdf, 2010.

M. Kirschbaum and T. Popp, Evaluation of a DPA-Resistant Prototype Chip, 2009 Annual Computer Security Applications Conference, 2009.
DOI : 10.1109/ACSAC.2009.14

S. S. Kumar, C. Paar, J. Pelzl, G. Pfeiffer, A. Rupp et al., How to Break DES for 8,980. Workshop on Special-purpose Hardware for Attacking Cryptographic Systems -SHARCS, 2006.

S. S. Kumar, C. Paar, J. Pelzl, G. Pfeiffer, and M. Schimmler, Breaking Ciphers with COPACOBANA ???A Cost-Optimized Parallel Code Breaker, Cryptographic Hardware and Embedded Systems ? CHES 2006, 8th International Workshop Proceedings, volume 4249 of Lecture Notes in Computer Science, pp.101-118, 2006.
DOI : 10.1007/11894063_9
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.105.7799

S. Mangard, E. Oswald, and T. Popp, Power Analysis Attacks ? Revealing the Secrets of Smart Cards, 2007.

S. Mangard, T. Popp, and B. M. Gammel, Side-Channel Leakage of Masked CMOS Gates, Proceedings, pp.351-365, 2005.
DOI : 10.1007/978-3-540-30574-3_24
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.695.326

S. Mangard, N. Pramstaller, and E. Oswald, Successfully Attacking Masked AES Hardware Implementations, Cryptographic Hardware and Embedded Systems ? CHES 2005, 7th International Workshop Proceedings, pp.157-171, 2005.
DOI : 10.1007/11545262_12
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.415.2680

D. May, H. L. Muller, and N. P. Smart, Non-deterministic Processors, Information Security and Privacy, 6th Australasian Conference Proceedings, volume 2119 of Lecture Notes in Computer Science, pp.115-129, 2001.
DOI : 10.1007/3-540-47719-5_11

D. Nakatsu, Y. Li, K. Sakiyama, and K. Ohta, Combination of SW Countermeasure and CPU Modification on FPGA against Power Analysis, Information Security Applications, 11th International Workshop, pp.258-272, 2010.
DOI : 10.1007/978-3-540-74735-2_4

P. Alfke, Xilinx Application note on Shift Registers and LFSR counters Available online at http://www.xilinx.com/support/documentation, 1996.

T. Popp, M. Kirschbaum, T. Zefferer, and S. Mangard, Evaluation of the Masked Logic Style MDPL on a Prototype Chip, Cryptographic Hardware and Embedded Systems ? CHES 2007, 9th International Workshop Proceedings, pp.81-94, 2007.
DOI : 10.1007/978-3-540-74735-2_6

T. Popp and S. Mangard, Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints, Cryptographic Hardware and Embedded Systems ? CHES 2005, 7th International Workshop Proceedings, pp.172-186, 2005.
DOI : 10.1007/11545262_13

F. Regazzoni, A. Cevrero, F. Standaert, S. Badel, T. Kluter et al., A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions, Cryptographic Hardware and Embedded Systems ? CHES 2009, 11th International Workshop Proceedings, pp.205-219, 2009.
DOI : 10.1007/978-3-642-04138-9_15
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.216.626

P. Schaumont and K. Tiri, Masking and Dual-Rail Logic Don???t Add Up, Cryptographic Hardware and Embedded Systems ? CHES 2007, 9th International Workshop Proceedings, pp.95-106, 2007.
DOI : 10.1007/978-3-540-74735-2_7
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.98.20

D. Suzuki and M. Saeki, Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style, Cryptographic Hardware and Embedded Systems ? CHES 2006, 8th International Workshop Proceedings, pp.255-269, 2006.
DOI : 10.1007/11894063_21
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.561.2405

S. Tillich and J. Großschädl, Power Analysis Resistant AES Implementation with Instruction Set Extensions, Cryptographic Hardware and Embedded Systems ? CHES 2007, 9th International Workshop Proceedings, pp.303-319, 2007.
DOI : 10.1007/978-3-540-74735-2_21
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.136.8272

S. Tillich, M. Kirschbaum, and A. Szekely, SCA-Resistant Embedded Processors? The Next Generation, 26th Annual Computer Security Applications Conference, pp.6-10, 2010.
DOI : 10.1145/1920261.1920293

K. Tiri and P. Schaumont, Changing the Odds Against Masked Logic, Selected Areas in Cryptography, 13th International Workshop, pp.134-146, 2006.
DOI : 10.1007/978-3-540-74462-7_10
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.96.1962

K. Tiri and I. Verbauwhede, A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation, Proceedings Design, Automation and Test in Europe Conference and Exhibition, pp.16-20, 2004.
DOI : 10.1109/DATE.2004.1268856
URL : http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.3.6040&rep=rep1&type=pdf

P. Yu and P. Schaumont, Secure FPGA circuits using controlled placement and routing, Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis , CODES+ISSS '07, pp.45-50, 2007.
DOI : 10.1145/1289816.1289831
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.380.1976