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Conference Papers Year : 2017

Netloc: a Tool for Topology-Aware Process Mapping

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Abstract

Interconnection networks in parallel platforms can be made of thousands of nodes and hundreds of switches. The communication cost between tasks of a parallel application varies significantly with their actual location in such platforms. Topology-aware process mapping consists in matching the application communication pattern with the network topology to improve the communication cost by placing related tasks close on the hardware. We show that our Netloc tool for gathering network topology in a generic way can be combined with the state-of-the-art Scotch partitioner for computing topology-aware MPI process placement. Our experiments with a stencil application on a fat-tree machine show that we are able to significantly improve the runtime in the vast majority of cases.
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Dates and versions

hal-01614437 , version 1 (10-10-2017)
hal-01614437 , version 2 (11-10-2017)

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Cyril Bordage, Clément Foyer, Brice Goglin. Netloc: a Tool for Topology-Aware Process Mapping. Euro-Par 2017: Parallel Processing Workshops, Aug 2017, Santiago de Compostela, Spain. ⟨10.1007/978-3-319-75178-8_13⟩. ⟨hal-01614437v2⟩
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