Simty: generalized SIMT execution on RISC-V

Sylvain Collange 1
1 PACAP - Pushing Architecture and Compilation for Application Performance
Inria Rennes – Bretagne Atlantique , IRISA_D3 - ARCHITECTURE
Abstract : We present Simty, a massively multi-threaded RISC-V processor core that acts as a proof of concept for dynamic inter-thread vector-ization at the micro-architecture level. Simty runs groups of scalar threads executing SPMD code in lockstep, and assembles SIMD instructions dynamically across threads. Unlike existing SIMD or SIMT processors like GPUs or vector processors, Simty vector-izes scalar general-purpose binaries. It does not involve any instruction set extension or compiler change. Simty is described in synthesizable RTL. A FPGA prototype validates its scaling up to 2048 threads per core with 32-wide SIMD units. Simty provides an open platform for research on GPU micro-architecture, on hybrid CPU-GPU micro-architecture, or on heterogeneous platforms with throughput-optimized cores.
Keywords : SIMT SIMD FPGA RISC-V
Type de document :
Communication dans un congrès
First Workshop on Computer Architecture Research with RISC-V (CARRV 2017), Oct 2017, Boston, United States. pp.6 2017, First Workshop on Computer Architecture Research with RISC-V
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Contributeur : Sylvain Collange <>
Soumis le : mardi 24 octobre 2017 - 11:03:34
Dernière modification le : jeudi 11 janvier 2018 - 02:09:28

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Sylvain Collange. Simty: generalized SIMT execution on RISC-V. First Workshop on Computer Architecture Research with RISC-V (CARRV 2017), Oct 2017, Boston, United States. pp.6 2017, First Workshop on Computer Architecture Research with RISC-V. 〈hal-01622208〉

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