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NEDA: NOP Exploitation with Dependency Awareness for Reliable VLIW Processors

Abstract : Critical applications require reliable processors that combine performance with low cost and energy consumption. Very Long Instruction Word (VLIW) processors have inherent resource redundancy not constantly used due to application's fluctuating Instruction Level Parallelism (ILP). Reliability through idle slots utilization is explored either at compile-time, increasing code size and storage requirements, or at run-time only inside the current instruction bundle, adding unnecessary time slots and degrading performance. To address this issue, we propose a technique to explore the idle slots inside and across original and replicated instruction bundles reclaiming more efficiently the idle slots and creating a compact schedule. To achieve this, a dependency analysis is applied at run-time. The execution of both original and replicated instructions is allowed at any adequate function unit, providing higher flexibility on instruction scheduling. The proposed technique achieves up to 26% reduction in performance degradation over existing approaches.
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https://hal.inria.fr/hal-01633770
Contributor : Olivier Sentieys <>
Submitted on : Tuesday, November 14, 2017 - 2:08:31 PM
Last modification on : Wednesday, June 24, 2020 - 4:19:45 PM
Document(s) archivé(s) le : Thursday, February 15, 2018 - 12:53:08 PM

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Rafail Psiakis, Angeliki Kritikakou, Olivier Sentieys. NEDA: NOP Exploitation with Dependency Awareness for Reliable VLIW Processors. ISVLSI 2017 - IEEE Computer Society Annual Symposium on VLSI, May 2017, Bochum, Germany. pp.391-396, ⟨10.1109/ISVLSI.2017.75⟩. ⟨hal-01633770⟩

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