F. Lemonnier, Towards future adaptive multiprocessor systemson-chip: an innovative approach for flexible architectures, Proc. IEEE Int. Conf. on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS), pp.1-6, 2012.
DOI : 10.1109/samos.2012.6404179
URL : http://www.es.ele.tue.nl/~kgoossens/2012-samos.pdf

A. Dorai, V. Fresse, C. Combes, E. Bourennane, and A. Mtibaa, A collision management structure for NoC deployment on multi-FPGA, Microprocessors and Microsystems, vol.49, pp.28-43, 2017.
DOI : 10.1016/j.micpro.2017.01.006
URL : https://hal.archives-ouvertes.fr/hal-01499098

Q. Tang, H. Mehrez, and M. Tuna, Multi-FPGA prototyping board issue: the FPGA I/O bottleneck, 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), pp.207-214, 2014.
DOI : 10.1109/SAMOS.2014.6893213
URL : https://hal.archives-ouvertes.fr/hal-01073937

U. Farooq, R. Chotin-avot, M. Azeem, M. Ravoson, M. Turki et al., Inter-FPGA routing environment for performance exploration of multi-FPGA systems, Proceedings of the 27th International Symposium on Rapid System Prototyping Shortening the Path from Specification to Prototype, RSP '16, pp.1-7, 2016.
DOI : 10.1109/RSP.2013.6683951
URL : https://hal.archives-ouvertes.fr/hal-01406803

F. Mao, W. Zhang, B. Feng, B. He, and Y. Ma, Modular Placement for Interposer based Multi-FPGA Systems, Proceedings of the 26th edition on Great Lakes Symposium on VLSI, GLSVLSI '16, pp.93-98, 2016.
DOI : 10.1145/157485.164669

J. Philippe, S. Pillement, and O. Sentieys, A low-power and highspeed quaternary interconnection link using efficient converters, Proc. of the IEEE International Symposium on Circuits and Systems, ISCAS'05, pp.4689-4692, 2005.
DOI : 10.1109/iscas.2005.1465679

M. Cannon, M. Wirthlin, A. Camplani, M. Citterio, and C. Meroni, Evaluating Xilinx 7 Series GTX Transceivers for Use in High Energy Physics Experiments Through Proton Irradiation, IEEE Transactions on Nuclear Science, vol.62, issue.6, pp.2695-2702, 2015.
DOI : 10.1109/TNS.2015.2497216

. Xilinx, Vc707 evaluation board for the virtex-7 fpga user guide, 2016.

A. B. Nejad, A. Molnos, M. E. Martinez, and K. Goossens, A hardware/software platform for QoS bridging over multi-chip NoC-based systems, Parallel Computing, vol.39, issue.9, pp.424-441, 2013.
DOI : 10.1016/j.parco.2013.04.011

X. Liu, Q. Deng, and Z. Wang, Design and FPGA Implementation of High-Speed, Fixed-Latency Serial Transceivers, IEEE Transactions on Nuclear Science, vol.61, issue.1, pp.561-567, 2014.
DOI : 10.1109/TNS.2013.2296301

A. Aloisio, R. Giordano, V. Izzo, and S. Perrella, A Frequency Agile, Self-Adaptive Serial Link on Xilinx FPGAs, IEEE Transactions on Nuclear Science, vol.62, issue.3, pp.955-962, 2015.
DOI : 10.1109/TNS.2015.2423674

N. Nedjah, L. S. Junior, and L. De-macedo-mourelle, Congestion-aware ant colony based routing algorithms for efficient application execution on Network-on-Chip platform, Expert Systems with Applications, vol.40, issue.16, pp.6661-6673, 2013.
DOI : 10.1016/j.eswa.2013.06.005

M. Ebrahimi, Fully adaptive routing algorithms and region-based approaches for two-dimensional and three-dimensional networks-on-chip, IET Computers & Digital Techniques, vol.7, issue.6, pp.264-273, 2013.
DOI : 10.1049/iet-cdt.2013.0034