HAL will be down for maintenance from Friday, June 10 at 4pm through Monday, June 13 at 9am. More information
Skip to Main content Skip to Navigation
Conference papers

Embedding the V-Detector Algorithm in FPGA

Abstract : The b-v model is a hybrid immune-based approach for detecting anomalies in high-dimensional datasets. It is based on a negative selection algorithm and utilizes both types of detectors to achieve better results in comparison to single detection models. Also, it is an interesting alternative to well known traditional, statistical approaches, because only positive (self) examples are required at the learning stage. As a result, it is able to detect even unnkown or never met anomalies and this fact is one of the most attractive features of this approach. However, especially in the case of on-line classification, not only high accuracy but also high efficiency is needed. Thus, we propose to embed some complex tasks in a reprogrammable FPGA to offload CPU and speed up the classification process. This paper presents a hardware implementation of the V-Detector algorithm, which is the most complex and time consuming part of b-v model.
Complete list of metadata

Cited literature [13 references]  Display  Hide  Download

Contributor : Hal Ifip Connect in order to contact the contributor
Submitted on : Friday, November 17, 2017 - 3:43:22 PM
Last modification on : Saturday, November 18, 2017 - 1:16:36 AM
Long-term archiving on: : Sunday, February 18, 2018 - 2:25:15 PM


Files produced by the author(s)


Distributed under a Creative Commons Attribution 4.0 International License




Maciej Brzozowski, Andrzej Chmielewski. Embedding the V-Detector Algorithm in FPGA. 15th IFIP International Conference on Computer Information Systems and Industrial Management (CISIM), Sep 2016, Vilnius, Lithuania. pp.43-54, ⟨10.1007/978-3-319-45378-1_5⟩. ⟨hal-01637459⟩



Record views


Files downloads