Embedding the V-Detector Algorithm in FPGA

Abstract : The b-v model is a hybrid immune-based approach for detecting anomalies in high-dimensional datasets. It is based on a negative selection algorithm and utilizes both types of detectors to achieve better results in comparison to single detection models. Also, it is an interesting alternative to well known traditional, statistical approaches, because only positive (self) examples are required at the learning stage. As a result, it is able to detect even unnkown or never met anomalies and this fact is one of the most attractive features of this approach. However, especially in the case of on-line classification, not only high accuracy but also high efficiency is needed. Thus, we propose to embed some complex tasks in a reprogrammable FPGA to offload CPU and speed up the classification process. This paper presents a hardware implementation of the V-Detector algorithm, which is the most complex and time consuming part of b-v model.
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Communication dans un congrès
Khalid Saeed; Władysław Homenda. 15th IFIP International Conference on Computer Information Systems and Industrial Management (CISIM), Sep 2016, Vilnius, Lithuania. Springer International Publishing, Lecture Notes in Computer Science, LNCS-9842, pp.43-54, 2016, Computer Information Systems and Industrial Management. 〈10.1007/978-3-319-45378-1_5〉
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Maciej Brzozowski, Andrzej Chmielewski. Embedding the V-Detector Algorithm in FPGA. Khalid Saeed; Władysław Homenda. 15th IFIP International Conference on Computer Information Systems and Industrial Management (CISIM), Sep 2016, Vilnius, Lithuania. Springer International Publishing, Lecture Notes in Computer Science, LNCS-9842, pp.43-54, 2016, Computer Information Systems and Industrial Management. 〈10.1007/978-3-319-45378-1_5〉. 〈hal-01637459〉

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