One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs

Abstract : Iterative stencils are kernels in various application domains such as numerical simulations and medical imaging, that merit FPGA acceleration. The best architecture depends on many factors such as the target platform, off-chip memory bandwidth, problem size, and performance requirements. We generate a family of FPGA stencil accelerators targeting emerging System on Chip platforms, (e.g., Xilinx Zynq or Intel SoC). Our designs come with design knobs to explore trade-offs. We also propose performance models to hone in on the most interesting design points, and show how they accurately lead to optimal designs. The optimal choice depends on problem sizes and performance goals.
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Communication dans un congrès
FPL - 27th International Conference on Field Programmable Logic and Applications, Sep 2017, Gand, Belgium. IEEE, 〈10.23919/FPL.2017.8056781〉
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Soumis le : lundi 11 décembre 2017 - 18:37:13
Dernière modification le : mercredi 16 mai 2018 - 11:24:13

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Gaël Deest, Tomofumi Yuki, Sanjay Rajopadhye, Steven Derrien. One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs. FPL - 27th International Conference on Field Programmable Logic and Applications, Sep 2017, Gand, Belgium. IEEE, 〈10.23919/FPL.2017.8056781〉. 〈hal-01655590〉

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