Characterization of silent stores, International Conference on Parallel Architectures and Compilation Techniques (PACT), 2000. ,
System-level power optimization, Proceedings of the 1999 international symposium on Low power electronics and design , ISLPED '99, 2000. ,
DOI : 10.1145/313817.313957
The gem5 simulator, ACM SIGARCH Computer Architecture News, vol.39, issue.2 ,
DOI : 10.1145/2024716.2024718
A characterization of the Rodinia benchmark suite with comparison to contemporary CMP workloads, IEEE International Symposium on Workload Characterization (IISWC'10), 2010. ,
DOI : 10.1109/IISWC.2010.5650274
Architecture and data migration methodology for L1 cache design with hybrid SRAM and volatile STT-RAM configuration. Microprocessors and Microsystems, 2016. ,
Magpie: System-level evaluation of manycore systems with emerging memory technologies, Workshop on Emerging Memory Solutions -Technology, Manufacturing, Architectures, Design and Test at Design Automation and Test in Europe -DATE'2017, 2017. ,
URL : https://hal.archives-ouvertes.fr/lirmm-01467328
A circuit-level performance, energy, and area model for emerging nonvolatile memory, IEEE Trans. on CAD of Integrated Circuits and Systems, issue.7, pp.31994-1007, 2012. ,
Energy dissipation in general purpose microprocessors, IEEE Journal of Solid-State Circuits, vol.31, issue.9, pp.1277-1284, 1996. ,
DOI : 10.1109/4.535411
Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation, Proceedings of the 47th Design Automation Conference on, DAC '10, 2010. ,
DOI : 10.1145/1837274.1837363
A 4ns, 0.9V write voltage embedded perpendicular STT-MRAM fabricated by MTJ-Last process, Proceedings of Technical Program, 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2014. ,
DOI : 10.1109/VLSI-TSA.2014.6839663
Cache revive, Proceedings of the 49th Annual Design Automation Conference on, DAC '12, 2012. ,
DOI : 10.1145/2228360.2228406
LLVM: A compilation framework for lifelong program analysis & transformation, International Symposium on Code Generation and Optimization, 2004. CGO 2004., p.75, 2004. ,
DOI : 10.1109/CGO.2004.1281665
Silent stores and store value locality, Transactions on Computers, vol.50, issue.11, 2001. ,
On the value locality of store instructions, International Symposium on Computer Architecture (ISCA), 2000. ,
STT-RAM based energy-efficiency hybrid cache for CMPs, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011. ,
DOI : 10.1109/VLSISoC.2011.6081626
MAC, Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design, ISLPED '12, 2012. ,
DOI : 10.1145/2333660.2333738
URL : https://hal.archives-ouvertes.fr/hal-00529679
Compiler-Assisted STT-RAM-Based Hybrid Cache for Energy Efficient Embedded Systems, Transactions on Very Large Scale Integration (VLSI) Systems, pp.22-2014 ,
DOI : 10.1109/TVLSI.2013.2278295
Code Motion for Migration Minimization in STT-RAM Based Hybrid Cache, 2012 IEEE Computer Society Annual Symposium on VLSI, 2012. ,
DOI : 10.1109/ISVLSI.2012.84
MGC: Multiple graph-coloring for non-volatile memory based hybrid Scratchpad Memory, 2012 16th Workshop on Interaction between Compilers and Computer Architectures (INTERACT), 2012. ,
DOI : 10.1109/INTERACT.2012.6339622
A Survey of Software Techniques for Using Non-Volatile Memories for Storage and Main Memory Systems, IEEE Transactions on Parallel and Distributed Systems, vol.27, issue.5, p.2016 ,
DOI : 10.1109/TPDS.2015.2442980
Hiroyuki Hara, and Shigeji Fujita. 7.5 a 3.3ns-access-time 71.2w/mhz 1mb embedded stt-mram using physically eliminated read-disturb scheme and normally-off memory architecture, p.2015 ,
NVSleep: Using non-volatile memory to enable fast sleep/wakeup of idle cores, 2014 IEEE 32nd International Conference on Computer Design (ICCD), 2014. ,
DOI : 10.1109/ICCD.2014.6974712
Data memory organization and optimizations in application-specific systems, IEEE Design & Test of Computers, vol.18, issue.3, 2001. ,
DOI : 10.1109/54.922803
Relaxing non-volatility for fast and energy-efficient STT-RAM caches, 2011 IEEE 17th International Symposium on High Performance Computer Architecture, 2011. ,
DOI : 10.1109/HPCA.2011.5749716
A novel architecture of the 3D stacked MRAM L2 cache for CMPs, 2009 IEEE 15th International Symposium on High Performance Computer Architecture, 2009. ,
DOI : 10.1109/HPCA.2009.4798259
Data-triggered threads: Eliminating redundant computation, 2011 IEEE 17th International Symposium on High Performance Computer Architecture, 2011. ,
DOI : 10.1109/HPCA.2011.5749727
Software data-triggered threads, Conference on Object-Oriented Programming, Systems, Languages, and Applications, OOPSLA, 2012. ,
CDTT: Compiler-generated data-triggered threads, 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA), 2014. ,
DOI : 10.1109/HPCA.2014.6835973
REDSPY: exploring value locality in software, International Conference on Architectural Support for Programming Languages and Operating Systems ASPLOS, 2017. ,
Power and performance of read-write aware hybrid caches with non-volatile memories, Design, Automation & Test in Europe Conference & Exhibition (DATE, 2009. ,
Energy reduction for STT-RAM using early write termination, Proceedings of the 2009 International Conference on Computer-Aided Design, ICCAD '09, 2009. ,
DOI : 10.1145/1687399.1687448