Optimizing DDR-SDRAM Communications at C-level for Automatically-Generated Hardware Accelerators : An Experience With the Altera C2H HLS Tool

Christophe Alias 1 Alain Darte 2 Alexandru Plesco 1
1 COMPSYS - Compilation and embedded computing systems
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
2 REMAP - Regularity and massive parallel computing
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : Thanks to efficient scheduling, resource sharing, and finite-state machines generation, high-level synthesis (HLS) tools are now more mature for generating hardware accelerators with an optimized internal structure. But interfacing them within the complete design, with optimized communications, to achieve the best throughput remains hard. Expert designers still need to program all the necessary glue (in VHDL/Verilog) to get an efficient design. Taking the example of C2H, the Altera HLS tool, and of accelerators communicating to an external DDR memory, we show it is possible to restructure the application code, to generate adequate communication processes, in C, and to compile them all with C2H, so that the resulting application is highly-optimized, with full usage of the memory bandwidth. In other words, our study demonstrates that HLS tools can be used as back-end optimizers for front-end optimizations, as it is the case for standard compilation with high-level transformations developed on top of assembly-code optimizers. We believe this is the way to go for making HLS tools viable.
Type de document :
Communication dans un congrès
IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'10), Jul 2010, Rennes, France
Liste complète des métadonnées

Littérature citée [9 références]  Voir  Masquer  Télécharger

https://hal.inria.fr/hal-01664033
Contributeur : Christophe Alias <>
Soumis le : jeudi 14 décembre 2017 - 14:37:08
Dernière modification le : vendredi 20 avril 2018 - 15:44:24

Fichier

asap2010.pdf
Fichiers produits par l'(les) auteur(s)

Identifiants

  • HAL Id : hal-01664033, version 1

Collections

Citation

Christophe Alias, Alain Darte, Alexandru Plesco. Optimizing DDR-SDRAM Communications at C-level for Automatically-Generated Hardware Accelerators : An Experience With the Altera C2H HLS Tool. IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'10), Jul 2010, Rennes, France. 〈hal-01664033〉

Partager

Métriques

Consultations de la notice

204

Téléchargements de fichiers

21