R. Mukundrajan, M. Cotter, V. Saripalli, M. Irwin, S. Datta et al., Ultra Low Power Circuit Design Using Tunnel FETs, 2012 IEEE Computer Society Annual Symposium on VLSI, pp.153-158, 2012.
DOI : 10.1109/ISVLSI.2012.70

M. S. Kim, H. Liu, K. Swaminathan, X. Li, S. Datta et al., Enabling Power-Efficient Designs with III-V Tunnel FETs, 2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), pp.1-4, 2014.
DOI : 10.1109/CSICS.2014.6978551

Y. Chen, M. Fan, V. Hu, P. Su, and C. Chuang, Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol.4, issue.4, pp.389-399, 2014.
DOI : 10.1109/JETCAS.2014.2361072

S. Migita, T. Matsukawa, T. Mori, K. Fukuda, Y. Morita et al., Variation behavior of tunnel-FETs originated from dopant concentration at source region and channel edge configuration, 2014 44th European Solid State Device Research Conference (ESSDERC), pp.278-281, 2014.
DOI : 10.1109/ESSDERC.2014.6948814

L. Zhang, M. Chan, and F. He, The impact of device parameter variation on double gate tunneling FET and double gate MOSFET, IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC), pp.1-4, 2010.

N. Damrongplasit, C. Shin, S. H. Kim, R. A. Vega, and T. K. Liu, Study of Random Dopant Fluctuation Effects in Germanium-Source Tunnel FETs, IEEE Transactions on Electron Devices, vol.58, issue.10, pp.3541-3548, 2011.
DOI : 10.1109/TED.2011.2161990

M. Hemmat, M. Kamal, A. Afzali-kusha, and M. Pedram, Study on the impact of device parameter variations on performance of III-V homojunction and heterojunction tunnel FETs, Solid-State Electronics, vol.124, pp.46-53, 2016.
DOI : 10.1016/j.sse.2016.06.010

M. Hemmat, M. Kamal, A. Afzali-kusha, and M. Pedram, Hybrid TFET-MOSFET circuits: An approach to design reliable ultra-low power circuits in the presence of process variation, 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp.1-6, 2016.
DOI : 10.1109/VLSI-SoC.2016.7753578

Y. S. Dhillon, A. U. Diril, and A. Chatterjee, Soft-error tolerance analysis and optimization of nanometer circuits, IEEE International conference on Design, Automation, and Test in Europe, pp.389-400, 2008.
URL : https://hal.archives-ouvertes.fr/hal-00181531

H. Liu, M. Cotter, S. Datta, and V. Narayanan, Technology assessment of Si and III-V FinFETs and III-V tunnel FETs from soft error rate perspective, 2012 International Electron Devices Meeting, 2012.
DOI : 10.1109/IEDM.2012.6479103

S. Datta, H. Liu, and V. Narayanan, Tunnel FET technology: A reliability perspective, Microelectronics Reliability, vol.54, issue.5, pp.861-874, 2014.
DOI : 10.1016/j.microrel.2014.02.002

M. Hemmat, M. Kamal, A. Afzali-kusha, and M. Pedram, Hybrid TFET-MOSFET circuit: A solution to design soft-error resilient ultra-low power digital circuit, Integration, the VLSI Journal, vol.57, pp.11-19, 2017.
DOI : 10.1016/j.vlsi.2016.11.001

A. Tura, Novel Vertical Tunnel Transistors for Continued Voltage Scaling, 2010.

A. Mishra, K. K. Jha, and M. Pattanaik, Parameter variation aware hybrid TFET-CMOS based power gating technique with a temperature variation tolerant sleep mode, Microelectronics Journal, vol.45, issue.11, pp.1515-1521, 2014.
DOI : 10.1016/j.mejo.2014.08.005

H. Liu and S. Datta, III-V Tunnel FET model manual. The Pennsylvania state university, 2015.

M. Cotter, H. Liu, S. Datta, and V. Narayanan, Evaluation of tunnel FET-based flip-flop designs for low power, high performance applications, International Symposium on Quality Electronic Design (ISQED), pp.430-437, 2013.
DOI : 10.1109/ISQED.2013.6523647

N. Miskov-zivanov and D. Marculescu, Modeling and optimization for soft-error reliability of sequential circuits. J. Computer-Aided Design of Integrated Circuits and Systems, pp.803-816, 2008.

S. Lin, Y. Kim, and F. Lombardi, Soft-Error Hardening Designs of Nanoscale CMOS Latches, 2009 27th IEEE VLSI Test Symposium, pp.27-41, 2009.
DOI : 10.1109/VTS.2009.10