G. Yuan, R. Alaa, and A. Taee, Design techniques for decision feedback equalization for multi-giga-bit-pe-second serial data links: a state-of-the-art review. IET Circuits, Devices ? Systems, pp.52-118, 2014.

J. Bulzacchelli, Equalization for Electrical Links: Current Design Techniques and Future Directions, IEEE Solid-State Circuits Magazine, vol.7, issue.4, pp.23-31, 2015.
DOI : 10.1109/MSSC.2015.2475996

X. Wang and Q. Hu, Analysis and optimization of combined equalizer for high speed serial link, 2015 IEEE 9th International Conference on Anti-counterfeiting, Security, and Identification (ASID), pp.2015-2058, 2015.
DOI : 10.1109/ICASID.2015.7405658

M. Pervez, Y. Cathy, and H. Adam, Partial response maximum likelihood equalization and detection for DSP based SerDes with cross talk and practical equalization, pp.1-27, 2014.

M. Pervez, Y. Cathy, and H. Adam, Partial response and noise predictive maximum likelihood (PRML/NPML) equalization and detection for high speed serial link systems, pp.1160-1184, 2013.

. R. Boesch, . K. Zheng, and . B. Murmann, A 0.003 mm 2 5.2 mW/tap 20 GBd inductor-less 5- tap analog RX-FFE, IEEE Symposium on VLSI Circuits, pp.1-2, 2016.

. N. Kocaman, T. Ali, and P. Rao, A 3.8 mW/Gbps quad-channel 8.5?13 Gbps serial link with a 5 tap DFE and a 4 tap transmit FFE in 28 nm CMOS, IEEE Journal of Solid-State Circuits, vol.51, issue.4, pp.881-892, 2016.

S. Kao and S. Liu, A 7.5-Gb/s One-Tap-FFE Transmitter With Adaptive Far-End Crosstalk Cancellation Using Duty Cycle Detection, IEEE Journal of Solid-State Circuits, vol.48, issue.2, pp.391-404, 2013.
DOI : 10.1109/JSSC.2012.2227604

URL : https://hal.archives-ouvertes.fr/in2p3-00553516

J. Preibisch, J. Reuschel, and K. Scharff, Impact of continuous time linear equalizer variability on eye opening of high-speed links, 2016 IEEE 20th Workshop on Signal and Power Integrity (SPI), pp.1-4, 2016.
DOI : 10.1109/SaPIW.2016.7496287

Z. Feng and Q. Hu, A 625 Gb/s decision feedback equalizer in 0.18 ?m CMOS technology for high-speed SerDes, 7th International Conference on Wireless Communications , Networking and Mobile Computing, pp.1-4, 2011.

S. Yuan, Z. Wang, and X. Zheng, A 10 Gb/s speculative decision feedback equalizer with a novel implementation of adaption in 65 nm CMOS technology, IEEE International Conference on Electron Devices and Solid-State Circuits, pp.1-2, 2014.

S. Parikh, T. Kao, Y. Hidaka, and J. Jiang, A 32 Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28 nm CMOS, IEEE Solid State Circuits Conference, pp.28-29, 2013.

R. Navid, E. Chen, and M. Hossain, A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology, IEEE Journal of Solid-State Circuits, vol.50, issue.4, pp.814-827, 2015.
DOI : 10.1109/JSSC.2014.2374176

G. Zhang, P. Chaudhair, and M. Green, A BiCMOS 10 Gb/s adaptive cable equalizer, IEEE Solid State Circuits Conference, pp.149-152, 2003.
DOI : 10.1109/iscas.2003.1205497

C. Jiang and Q. Hu, A 625 Gb/s adaptive analog equalizer in 0.18 ?m CMOS technology for high-speed SerDes, 2012 2nd International Conference on Computer Science and Network Technology, pp.266-270, 2012.

Y. Kim, T. Lee, and L. Kim, A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.24, issue.2, pp.789-793, 2016.
DOI : 10.1109/TVLSI.2015.2418579

S. Ibrahim and B. Razavi, Low-Power CMOS Equalizer Design for 20-Gb/s Systems, IEEE Journal of Solid-State Circuits, vol.46, issue.6, pp.1321-1336, 2011.
DOI : 10.1109/JSSC.2011.2134450