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Karatsuba with Rectangular Multipliers for FPGAs
Abstract : This work presents an extension of Karatsuba's method to efficiently use rectangular multipliers as a base for larger multipliers. The rectangular multipliers that motivate this work are the embedded 18×25-bit signed multipliers found in the DSP blocks of recent Xilinx FPGAs: The traditional Karatsuba approach must under-use them as square 18×18 ones. This work shows that rectangular multipliers can be efficiently exploited in a modified Karatsuba method if their input word sizes have a large greatest common divider. In the Xilinx FPGA case, this can be obtained by using the embedded multipliers as 16×24 unsigned and as 17×25 signed ones. The obtained architectures are implemented with due detail to architectural features such as the pre-adders and post-adders available in Xilinx DSP blocks. They are synthesized and compared with traditional Karatsuba, but also with (non-Karatsuba) state-of-the-art tiling techniques that make use of the full rectangular multipliers. The proposed technique improves resource consumption and performance for multipliers of numbers larger than 64 bits.
Cited literature [16 references]
https://hal.inria.fr/hal-01773447
Contributor : Florent de Dinechin <>
Submitted on : Saturday, April 21, 2018 - 11:58:35 PM
Last modification on : Tuesday, November 19, 2019 - 12:09:38 PM
Document(s) archivé(s) le : Tuesday, September 18, 2018 - 10:26:37 PM
Contributor : Florent de Dinechin <>
Submitted on : Saturday, April 21, 2018 - 11:58:35 PM
Last modification on : Tuesday, November 19, 2019 - 12:09:38 PM
Document(s) archivé(s) le : Tuesday, September 18, 2018 - 10:26:37 PM
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