A. Karatsuba and Y. Ofman, Multiplication of multidigit numbers on automata, Soviet Physics Doklady, vol.7, p.595, 1963.

F. De-dinechin and B. Pasca, Large multipliers with fewer DSP blocks, 2009 International Conference on Field Programmable Logic and Applications, pp.250-255, 2009.
DOI : 10.1109/FPL.2009.5272296

B. Pasca, High-performance floating-point computing on reconfigurable circuits, 2012.
URL : https://hal.archives-ouvertes.fr/tel-00654121

G. I. Malaschonok and E. Satina, Fast Multiplication and Sparse Structures, Programming and Computer Software, vol.30, issue.2, pp.105-109, 2004.
DOI : 10.1023/B:PACS.0000021269.20049.0f

J. Van-der-hoeven and G. Lecerf, On the bit-complexity of sparse polynomial and series multiplication, Journal of Symbolic Computation, vol.50, pp.227-254, 2013.
DOI : 10.1016/j.jsc.2012.06.004
URL : https://hal.archives-ouvertes.fr/hal-00476223

C. Moore, N. Hanley, J. Mcallister, M. O. Neill, E. O. Sullivan et al., Targeting FPGA DSP Slices for a Large Integer Multiplier for Integer Based FHE, Financial Cryptography and Data Security, pp.226-237, 2013.
DOI : 10.1007/978-3-642-41320-9_16
URL : https://pure.qub.ac.uk/portal/files/17926311/targeting.pdf

S. Gao, D. Al-khalili, N. Chabini, and P. Langlois, Asymmetric large size multipliers with optimised FPGA resource utilisation, IET Computers & Digital Techniques, vol.6, issue.6, pp.372-383, 2012.
DOI : 10.1049/iet-cdt.2011.0146

M. Kumm, J. Kappauf, M. Istoan, and P. Zipf, Resource Optimal Design of Large Multipliers for FPGAs, 2017 IEEE 24th Symposium on Computer Arithmetic (ARITH), pp.131-138, 2017.
DOI : 10.1109/ARITH.2017.35

M. K. Jaiswal and R. C. Cheung, VLSI Implementation of Double-Precision Floating-Point Multiplier Using Karatsuba Technique, Circuits, Systems, and Signal Processing, pp.15-27, 2012.
DOI : 10.1145/1839480.1839486

P. L. Montgomery, Five, six, and seven-term Karatsuba-like formulae, IEEE Transactions on Computers, vol.54, issue.3, pp.362-369, 2005.
DOI : 10.1109/TC.2005.49
URL : http://www.csd.uwo.ca/%7Eeschost/Exam/Montgomery--Five_six_and_seven_terms_Karatsuba-like_formulae.pdf

R. Brent and P. Zimmermann, Modern Computer Arithmetic, 2010.
DOI : 10.1017/CBO9780511921698
URL : https://hal.archives-ouvertes.fr/cel-01500109

M. Bodrato and A. Zanoni, Integer and polynomial multiplication, Proceedings of the 2007 international symposium on Symbolic and algebraic computation , ISSAC '07, pp.17-24, 2007.
DOI : 10.1145/1277548.1277552

H. F. Ugurdag, F. De-dinechin, Y. S. Gener, S. Gren, and L. Didier, Hardware Division by Small Integer Constants, IEEE Transactions on Computers, vol.66, issue.12, pp.2097-2110, 2017.
DOI : 10.1109/TC.2017.2707488
URL : https://hal.archives-ouvertes.fr/hal-01402252

F. De-dinechin and B. Pasca, Custom arithmetic datapath design for FPGAs using the FloPoCo core generator, IEEE Design & Test of Computers, issue.99, pp.1-1, 2012.

N. Brunie, F. De-dinechin, M. Istoan, G. Sergent, K. Illyes et al., Arithmetic core generation using bit heaps, 2013 23rd International Conference on Field programmable Logic and Applications, pp.1-8, 2013.
DOI : 10.1109/FPL.2013.6645544
URL : https://hal.archives-ouvertes.fr/ensl-00738412

M. Kumm and J. Kappauf, Advanced Compressor Tree Synthesis for FPGAs, IEEE Transactions on Computers, pp.1-1, 2018.
DOI : 10.1109/TC.2018.2795611